TMS320DM640AZNZ4 Datasheet, PDF (105/179 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processors

External Memory Interface (EMIIF)
4.8.3 EMIF Electrical Data/Timing
4.8.3.1 Asynchronous Memory Timing
Table 4−22. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module^†‡
(see Figure 4−19 and Figure 4−20)
−400
−500
NO.
−600
UNIT
MIN MAX
3
t_su(EDV-AREH)
Setup time, AEDx valid before AARE high
6.5
ns
4
t_h(AREH-EDV)
Hold time, AEDx valid after AARE high
1
ns
6
t_{su(ARDY-EKO1H)}
Setup time, AARDY valid before AECLKOUTx high
3
ns
7
t_{h(EKO1H-ARDY)}
Hold time, AARDY valid after AECLKOUTx high
2.5
ns
† _{To ensure data setup time, simply program the strobe width wide enough. AARDY is internally synchronized. The AARDY signal is only}
recognized two cycles before the end of the programmed strobe time and while AARDY is low, the strobe time is extended cycle-by-cycle. When
AARDY is recognized low, the end of the strobe time is two cycles after AARDY is recognized high. To use AARDY as an asynchronous input,
the pulse width of the AARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met.
‡ _{RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are}
programmed via the EMIF CE space control registers.
Table 4−23. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for EMIFA Module^{‡§¶} (see Figure 4−19 and Figure 4−20)
NO.
PARAMETER
−400
−500
−600
UNIT
MIN MAX
1
t_{osu(SELV-AREL)}
Output setup time, select signals valid to AARE low
RS * E − 1.8
ns
2
t_{oh(AREH-SELIV)}
Output hold time, AARE high to select signals invalid
RH * E − 1.9
ns
5
t_{d(EKO1H-AREV)}
Delay time, AECLKOUTx high to AARE valid
1
7 ns
8
t_{osu(SELV-AWEL)}
Output setup time, select signals valid to AAWE low
WS * E − 2.0
ns
9
t_{oh(AWEH-SELIV)}
Output hold time, AAWE high to select signals invalid
WH * E − 2.5
ns
10 t_{d(EKO1H-AWEV)}
Delay time, AECLKOUTx high to AAWE valid
1.3
7.1 ns
‡ _{RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are}
programmed via the EMIF CE space control registers.
§ _{E = AECLKOUT1 period in ns for EMIFA}
¶ _{Select signals for EMIFA include: ACEx, ABE[3:0], AEA[22:3], AAOE; and for EMIFA writes, include AED[31:0].}
June 2003 − Revised October 2010
SPRS222F 105