TMS320DM640AZNZ4 Datasheet, PDF (119/179 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processors

External Memory Interface (EMIIF)
4.8.3.5 BUSREQ Timing
Table 4−30. Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles
for EMIFA Module (see Figure 4−33)
NO.
1
t_{d(AEKO1H-ABUSRV)}
PARAMETER
Delay time, AECLKOUTx high to ABUSREQ valid
−400
−500
MIN MAX
0.6 7.1
−600
MIN MAX
1 5.5
UNIT
ns
AECLKOUTx
ABUSREQ
1
1
Figure 4−33. BUSREQ Timing for EMIFA
June 2003 − Revised October 2010
SPRS222F 119