TMS320C6421_15 Datasheet, PDF (99/222 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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TMS320C6421
Fixed-Point Digital Signal Processor
SPRS346D – JANUARY 2007 – REVISED JUNE 2008
Table 3-38 shows the pin multiplexing control for each pin in the EMIFA Sub-Block 0. These PINMUX0
and PINMUX1 register fields control the multiplexing in this sub-block:
• PINMUX0: AEM, RMII
Table 3-39 shows the pin multiplexing control for each pin in the EMIFA Sub-Block 1. These PINMUX0
register fields control the multiplexing in this sub-block:
• PINMUX0: AEM, CS5SEL, CS4SEL, CS3SEL, RMII
EMIFA Sub-Block 2 is dedicated to EMIFA pins EM_WAIT/(RDY/BSY), EM_OE, and EM_WE. There is no
pin multiplexing in this block. These pins always function as EMIFA control pins.
Table 3-40 shows the pin multiplexing control for each pin in the EMIFA Sub-Block 3. These PINMUX0
and PINMUX1 register fields control the multiplexing in this sub-block:
• PINMUX0: AEM
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Device Configurations
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