TMS320C6421_15 Datasheet, PDF (96/222 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C6421
Fixed-Point Digital Signal Processor
SPRS346D – JANUARY 2007 – REVISED JUNE 2008
www.ti.com
In addition, the VDD3P3V_PWDN.PWM1 field determines the power state of the PWM1 Block pin. The
PWM1 Block pin defaults to powered down and not operational. To use this pin, user must first program
VDD3P3V_PWDN.PWM1 = 0 to power up the pin. For more details on the VDD3P3V_PWDN.PWM1 field,
see Section 3.2, Power Considerations.
3.7.3.10 CLKOUT Block
This block of 1 pin consists of CLKOUT, PWM2, and GPIO muxed pin (CLKOUT0/PWM2/GP[84]). The
PINMUX1.CKOBK register field selects the pin function in the CLKOUT Block.
Table 3-35 summarizes the 1 pin in the CLKOUT Block, its multiplexed function, and the PINMUX
configurations to select the corresponding function.
SIGNAL
NAME
CLKOUT0/
PWM2/
GP[84]
Table 3-35. CLKOUT Block Multiplexed Pin Selection
CLKOUT0
FUNCTION
SELECT
MULTIPLEXED FUNCTIONS
PWM2
FUNCTION
SELECT
GPIO
FUNCTION
SELECT
CLKOUT0
CKOBK = 01
PWM2
CKOBK = 10
GP[84]
CKOBK = 00
Table 3-36 provides a different view of the CLKOUT Block pin muxing, showing the CLKOUT Block
function based on PINMUX1.CKOBK setting. The selection options are also shown pictorially in
Figure 3-10.
PINMUX1.CKOBK
00
01
10
11
Table 3-36. CLKOUT Block Function Selection
BLOCK FUNCTION
GPIO (1)
CLKOUT (default)
PWM2
Reserved
RESULTING PIN FUNCTIONS
GPIO: GP[84]
Device Clock-Out: CLKOUT0
PWM2: PWM2
Reserved
This block defaults to CLKOUT0 pin function.
In addition, the VDD3P3V_PWDN.CLKOUT field determines the power state of the CLKOUT Block pin.
The CLKOUT Block pin defaults to powered up. For more details on the VDD3P3V_PWDN.CLKOUT field,
see Section 3.2, Power Considerations.
3.7.3.11 EMIFA Block Muxing
This block of 61 pins consists of EMIFA, EMAC(RMII), and GPIO muxed pins. The following register fields
affect the pin functions in the EMIFA Block:
• All PINMUX0 register fields: AEM, CS5SEL, CS4SEL, CS3SEL, and RMII.
There is only one EMAC peripheral on the C6421 device, even though the pins for MII mode and the pins
for RMII modes are brought out to different locations. The EMAC MII mode pins are in the Host Block,
while EMAC RMII mode pins are only in the EMIFA Block. The user is only allowed to select either the MII
pins or the RMII pins. The operation is undefined if the user attempts to select both MII pins and RMII
pins.
The EMIFA Block is divided into multiple sub-blocks for ultimate flexibility in pin multiplexing to
accommodate a wide variety of applications, and for the purpose of I/O pins power control:
• Sub-Block 0: multiplexed between EMIFA address/control pins, part of EMAC(RMII), and GPIO.
• Sub-Block 1: multiplexed between EMIFA data/address/control pins, part of EMAC(RMII), and GPIO.
• Sub-Block 2: no multiplexing. EMIFA control pins EM_WAIT/(RDY/BSY), EM_OE, EM_WE.
• Sub-Block 3: multiplexed between EMIFA address pins EM_A[12:6] and GPIO.
96
Device Configurations
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