TMS320C6421_15 Datasheet, PDF (90/222 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C6421
Fixed-Point Digital Signal Processor
SPRS346D – JANUARY 2007 – REVISED JUNE 2008
www.ti.com
SIGNAL NAME
VLYNQ_CLOCK/GP[57]
HD0/VLYNQ_SCRUN/GP[58]
HD1/VLYNQ_RXD0/GP[59]
HD2/VLYNQ_RXD1/GP[60]
HD3/VLYNQ_RXD2/GP[61]
HD4/VLYNQ_RXD3/GP[62]
HD5/VLYNQ_TXD0/GP[63]
HD6/VLYNQ_TXD1/GP[64]
HD7/VLYNQ_TXD2/GP[65]
HD8/VLYNQ_TXD3/GP[66]
HD9/MCOL/GP[67]
HD10/MCRS/GP[68]
HD11/MTXD3/GP[69]
HD12/MTXD2/GP[70]
HD13/MTXD1/GP[71]
HD14/MTXD0/GP[72]
HD15/MTXCLK/GP[73]
HHWIL/MRXDV/GP[74]
HCNTL1/MTXEN/GP[75]
HCNTL0/MRXER/GP[76]
HR/W/MRXCLK/GP[77]
HDS2/MRXD0/GP[78]
HDS1/MRXD1/GP[79]
HRDY/MRXD2/GP[80]
HCS/MDCLK/GP[81]
HINT/MRXD3/GP[82]
HAS/MDIO/GP[83]
Table 3-20. Host Block Muxed Pins Selection
HPI
FUNCTION
SELECT
–
–
HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
HD8
HD9
HD10
HD11
HD12
HD13
HD14
HD15
HHWIL
HCNTL1
HCNTL0
HR/W
HDS2
HDS1
HRDY
HCS
HINT
HAS
HOSTBK = 001
MULTIPLEXED FUNCTIONS
EMAC(MII)/MDIO
VLYNQ
FUNCTION
SELECT
FUNCTION
SELECT
–
–
VLYNQ_CLOCK
–
–
–
–
–
–
–
–
–
MCOL
MCRS
MTXD3
MTXD2
MTXD1
MTXD0
MTXCLK
MRXDV
MTXEN
MRXER
MRXCLK
MRXD0
MRXD1
MRXD2
MDCLK
MRXD3
MDIO
–
–
–
–
–
–
–
–
–
HOSTBK = 011
or
HOSTBK = 100
VLYNQ_SCRUN
VLYNQ_RXD0
VLYNQ_RXD1
VLYNQ_RXD2
VLYNQ_RXD3
VLYNQ_TXD0
VLYNQ_TXD1
VLYNQ_TXD2
VLYNQ_TXD3
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
HOSTBK = 010
or
HOSTBK = 011
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
GPIO
FUNCTION
SELECT
GP[57]
HOSTBK = 000
or
HOSTBK = 001
or
HOSTBK = 100
GP[58]
GP[59]
GP[60]
GP[61]
GP[62]
GP[63]
HOSTBK = 000
or
HOSTBK = 100
GP[64]
GP[65]
GP[66]
GP[67]
GP[68]
GP[69]
GP[70]
GP[71]
GP[72]
GP[73]
GP[74]
GP[75]
GP[76]
HOSTBK = 000
or
HOSTBK = 010
GP[77]
GP[78]
GP[79]
GP[80]
GP[81]
GP[82]
GP[83]
There is only one EMAC peripheral on the C6421 device, even though the pins for MII mode and the pins
for RMII modes are brought out to different locations. The EMAC MII mode pins are in the Host Block,
while EMAC RMII mode pins are only in the EMIFA Block. The user is only allowed to select either the MII
pins or the RMII pins. The operation is undefined if the user attempts to select both MII pins and RMII
pins.
Table 3-21 provides a different view of the Host Block pin muxing, showing the Host Block function based
on PINMUX1 settings. The selection options are also shown pictorially in Figure 3-10.
If EMAC operation is desired, EMAC must be placed in reset before programming PINMUX1.HOSTBK to
select EMAC pins.
PINMUX1
SETTING
HOSTBK
000
001
Table 3-21. Host Block Function Selection
BLOCK FUNCTION
GPIO (27)
(Default)
HPI + GPIO (1)
RESULTING PIN FUNCTIONS
GPIO: GP[83:57]
HPI: HHWIL, HCNTL[1:0], HR/W, HDS2, HDS1, HRDY, HCS, HINT, HAS, HD[15:0]
GPIO: GP[57]
90
Device Configurations
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