TMS320C6421_15 Datasheet, PDF (188/222 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C6421
Fixed-Point Digital Signal Processor
SPRS346D – JANUARY 2007 – REVISED JUNE 2008
www.ti.com
Table 6-52. Switching Characteristics Over Recommended Operating Conditions for McASP⁽¹⁾⁽²⁾
(see Figure 6-32 and Figure 6-33)⁽³⁾
-7/-6/-5/-4
NO.
PARAMETER
-L/-Q6/-Q5/-Q4 _UNIT
MIN MAX
9
t_c(AHCKRX)
10 t_w(AHCKRX)
11 t_c(CKRX)
12 t_w(CKRX)
Cycle time, AHCLKR/X
Pulse duration, AHCLKR/X high or low
Cycle time, ACLKR/X⁽⁴⁾
Pulse duration, ACLKR/X high or low
ACLKR/X int
ACLKR/X int
ACLKR/X int
25
AH -
2.5
25
A - 2.5
-2.25
ns
ns
ns
ns
5.5 ns
13 t_d(CKRX-FRX)
Delay time, ACLKR/X transmit edge to AFSX/R output valid
ACLKR/X
ext input
ACLKR/X
ext output
0 12.5 ns
0
14 ns
ACLKX int
-2.25 5.5 ns
14 t_d(CKX-AXRV)
Delay time, ACLKX transmit edge to AXR output valid
ACLKX
ext input
ACLKX
ext output
0 12.5 ns
0
14 ns
15 t_{dis(CKRX-AXRHZ)}
Disable time, AXR high impedance following last data bit from ^{ACLKR/X int}
ACLKR/X transmit edge
ACLKR/X ext
-4.5
8 ns
-4.5 12.5 ns
(1) A = (ACLKR/X period)/2 in ns. For example, when ACLKR/X period is 25 ns, use A = 12.5 ns.
(2) AH = (AHCLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
(3) ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
(4) There is a clock ratio requirement between the system infrastructure clock, SYSCLK3, and the McASP0 bit clocks, ACLKR/ACLKX. For
proper device operation, the ACLKR/ACLKX frequency must be no faster than of SYSCLK3 frequency.
188 Peripheral Information and Electrical Specifications
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