TMS320C6421_15 Datasheet, PDF (201/222 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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TMS320C6421
Fixed-Point Digital Signal Processor
SPRS346D – JANUARY 2007 – REVISED JUNE 2008
6.16.2 Management Data Input/Output (MDIO) Electrical Data/Timing
Table 6-65. Timing Requirements for MDIO Input (see Figure 6-41 and Figure 6-42)
NO.
1 t_c(MDCLK)
2 t_w(MDCLK)
3 t_t(MDCLK)
4 t_{su(MDIO-MDCLKH)}
5 t_{h(MDCLKH-MDIO)}
Cycle time, MDCLK
Pulse duration, MDCLK high/low
Transition time, MDCLK
Setup time, MDIO data input valid before MDCLK high
Hold time, MDIO data input valid after MDCLK high
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
MIN MAX
400
180
5
10
10
UNIT
ns
ns
ns
ns
ns
MDCLK
1
3
3
4
5
MDIO
(input)
Figure 6-41. MDIO Input Timing
Table 6-66. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
(see Figure 6-42)
NO.
7 t_{d(MDCLKL-MDIO)}
Delay time, MDCLK low to MDIO data output valid
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
MIN MAX
100
UNIT
ns
1
MDCLK
7
MDIO
(output)
Figure 6-42. MDIO Output Timing
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Peripheral Information and Electrical Specifications 201