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TMS320C6421_15 Datasheet, PDF (203/222 Pages) Texas Instruments – Fixed-Point Digital Signal Processor
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TMS320C6421
Fixed-Point Digital Signal Processor
SPRS346D – JANUARY 2007 – REVISED JUNE 2008
HEX ADDRESS RANGE
0x01C2 1C00
0x01C2 1C04
0x01C2 1C10
0x01C2 1C14
0x01C2 1C18
0x01C2 1C1C
0x01C2 1C20
0x01C2 1C24
0x01C2 1C28
0x01C2 1C2C - 0x01C2 1FFF
Table 6-69. Timer 2 (Watchdog) Registers
ACRONYM
-
EMUMGT_CLKSPD
TIM12
TIM34
PRD12
PRD34
TCR
TGCR
WDTCR
-
DESCRIPTION
Reserved
Timer 2 Emulation Management/Clock Speed Register
Timer 2 Counter Register 12
Timer 2 Counter Register 34
Timer 2 Period Register 12
Timer 2 Period Register 34
Timer 2 Control Register
Timer 2 Global Control Register
Timer 2 Watchdog Timer Control Register
Reserved
6.17.2 Timer Electrical Data/Timing
Table 6-70. Timing Requirements for Timer Input(1)(2)(3) (see Figure 6-43)
NO.
1 tw(TINPH) Pulse duration, TINPxL high
2 tw(TINPL) Pulse duration, TINPxL low
TINP0L, if TIMERCTL.TINP0SEL = 0
[default]
TINP0L, if TIMERCTL.TINP0SEL = 1
TINP1L
TINP0L, if TIMERCTL.TINP0SEL = 0
[default]
TINP0L, if TIMERCTL.TINP0SEL = 1
TINP1L
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4 UNIT
MIN MAX
2P
ns
0.33P
ns
2P
ns
2P
ns
0.33P
ns
2P
ns
(1) P = MXI/CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is 25 MHz, use P = 40 ns.
(2) The TIMERCTL.TINP0SEL field in the System Module determines if the TINP0L input directly goes to Timer 0
(TIMERCTL.TINP0SEL=0), or if the TINP0L input is first divided down by 6 before going to Timer 0 (TIMERCTL.TINP0SEL=1).
(3) TINP1L input goes directly to Timer 1.
Table 6-71. Switching Characteristics Over Recommended Operating Conditions for Timer Output(1) (see
Figure 6-43)
NO.
3 tw(TOUTH)
Pulse duration, TOUTxL high
4 tw(TOUTL)
Pulse duration, TOUTxL low
(1) P = MXI/CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is 25 MHz, use P = 40 ns.
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
MIN MAX
P
P
UNIT
ns
ns
TINPxL
1
2
TOUTxL
3
4
Figure 6-43. Timer Timing
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Peripheral Information and Electrical Specifications 203
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