TMS320C6421_15 Datasheet, PDF (71/222 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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Bit
Field Name
14:12 PLLMS
11
RSV
TMS320C6421
Fixed-Point Digital Signal Processor
SPRS346D – JANUARY 2007 – REVISED JUNE 2008
Table 3-7. BOOTCFG Register Description (continued)
Description
Fastboot PLL Multiplier Select [PLLMS] (see Section 3.5.1.2, Fast Boot PLL Multiplier Select [PLLMS])
If FASTBOOT = 1, this field selects the FASTBOOT PLL Multiplier according to Table 3-6.
The default value is latched from the PLLMS[2:0] configuration pins.
Reserved. Writes have no effect.
PINMUX0.AEM default [DAEM] (see Section 3.5.1.1, EMIFA Pinout Mode (AEM[2:0]))
10:8
DAEM
For more details on the AEM settings, see Section 3.7.2.1, PINMUX0 Register Description.
This field affects pin mux control by setting the default of PINMUX0.AEM. This field does not affect EMIFA
Register settings.
The default value is latched from the AEM[2:0] configuration pins.
7:4
RESERVED Reserved. Writes have no effect.
Boot Mode (see Section 3.4.1, Boot Modes)
3:0
BOOTMODE This field is used in conjunction with FASTBOOT and PLLMS to determine the device boot mode.
The default value is latched from the BOOTMODE[3:0] configuration pins.
3.4.2.2 BOOTCMPLT Register
If the bootloader code detects an error during boot, it records the error status in the Boot Complete
(BOOTCMPLT) register.
In addition, the BOOTCMPLT register is used for communication between the external host and the
bootloader code during a Host Boot (HPI Boot). Once the external host has completed boot, it must
perform the following communication with the bootloader code:
• Write the desired 32-bit CPU starting address in the DSPBOOTADDR register (see Section 3.4.2.3,
DSPBOOTADDR Register).
• Write a ‘1’ to the Boot Complete (BC) bit field in the BOOTCMPLT register to indicate that the host has
completed booting this device.
Once the bootloader code detects BC = 1, it directs the CPU to begin executing from the
DSPBOOTADDR register.
The BOOTCMPLT register is reset by any device-level global reset. For the list of device-level global
resets, see Section 6.5, Reset.
31
20
19
16
RESERVED
ERR
R/W-0000 0000 0000
R/W-0000
15
RESERVED
R/W- 0000 0000 0000 000
LEGEND: R = Read; W = Write; -n = value after reset
Figure 3-3. BOOTCMPLT Register— 0x01C4 000C
1
0
BC
R/W-0
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Device Configurations
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