DAC38RF82_17 Datasheet, PDF (99/140 Pages) Texas Instruments – Dual-Channel, Differential-Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface, On-Chip PLL and Wide-Band Interpolation

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DAC38RF82, DAC38RF89
SLASEA6B – FEBRUARY 2017 – REVISED AUGUST 2017
8.5.53 JESD Error Output Register (address = 0x52) [reset = 0x00FF]
Figure 104. JESD Error Output Register (JESD_ERR_OUT)
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
0
1
0
1
0
0
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 100. JESD_ERR_OUT Field Descriptions
Bit
15:10
9
8
Field
Reserved
DISABLE_ERR_RPT
PHADJ
7:0 ERR_ENA
Type
R/W
R/W
R/W
R/W
Reset
000000
0
0
0xFF
Description
Reserved
Assertion means that errors will not be reported on the sync_n
output.
Lane configuration
These bits select the errors generated are counted in the err_c
for the link. The bits also control what signals are sent out the
pad_syncb pin for error notification.
bit 7 = multi-frame alignment error
bit 6 = frame alignment error
bit 5 = link configuration error
bit 4 = elastic buffer overflow (bad RBD value)
bit 3 = elastic buffer end char mismatch (match_ctrl match_data)
bit 2 = code synchronization error
bit 1 = 8b/10b not-in-table code error
bit 0 = 8b/10b disparity error
8.5.54 JESD ILA Check 1 Register (address = 0x53) [reset = 0x0100]
Figure 105. JESD ILA Check 1 Register (JESD_ILA_CFG1)
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
0
1
0
1
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
15:8 ILA_M
7:0 ILA_F
Table 101. JESD_ILA_CFG1 Field Descriptions
Type
R/W
R/W
Reset
0x01
0x00
Description
JESD M-1 configuration value used only for ILA checking; may
be set independently of the actual JESD mode
JESD F-1 configuration value used only for ILA checking; may
be set independently of the actual JESD mode
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