DAC38RF82_17 Datasheet, PDF (133/140 Pages) Texas Instruments – Dual-Channel, Differential-Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface, On-Chip PLL and Wide-Band Interpolation

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Layout Guidelines (continued)
DAC38RF82, DAC38RF89
SLASEA6B – FEBRUARY 2017 – REVISED AUGUST 2017
Figure 150. Bypass Capacitors Placed on the Power Supply Pin With In-pad Vias
• High speed SerDes traces
– Route all SerDes traces straight and minimized sharp curves or serpentines. Route for best signal integrity
– Some skew between SerDes traces can be tolerated. It is recommended to limit skew between traces to
320ps or less
– Place ground planes between the SerDes traces for improved isolation
Figure 151. Layout Example of High Speed SerDes Traces
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