DAC38RF82_17 Datasheet, PDF (56/140 Pages) Texas Instruments – Dual-Channel, Differential-Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface, On-Chip PLL and Wide-Band Interpolation

DAC38RF82, DAC38RF89
SLASEA6B – FEBRUARY 2017 – REVISED AUGUST 2017
www.ti.com
The sampling is controlled by the serial interface signals SDEN and SCLK. If the temperature sensor is enabled
by writing a 0 to field TSENSE_SLEEP in register SLEEP_CONFIG (8.5.70), a conversion takes place each time
the serial port is written or read. The data is only read and sent out by the digital block when the temperature
sensor is read in field TEMPDATA in register TEMP_PLLVOLT (8.5.7). The conversion uses the first eight clocks
of the serial clock as the capture and conversion clock, the data is valid on the falling eighth SCLK. The data is
then clocked out of the chip on the rising edge of the ninth SCLK. No other clocks to the chip are necessary for
the temperature sensor operation. As a result the temperature sensor is enabled even when the device is in
sleep mode.
In order for the process described above to operate properly, the serial port read from register TEMP_PLLVOLT
must be done with an SCLK period of at least 1 μs. If this is not satisfied the temperature sensor accuracy is
greatly reduced.
8.3.25 Alarm Monitoring
The DAC38RF82 (or DAC38RF89) includes a flexible set of alarm monitoring that can be used to alert of a
possible malfunction scenario. All the alarm events can be accessed either through the SIP registers and/or
through the ALARM output. Once an alarm is set, the corresponding alarm bit must be reset through the serial
interface to allow further testing. The set of alarms includes the following conditions:
• JESD alarms
– Fields ALM_LANEx_ERR in registers JESD_ALM_Lx (x = 0-7, 8.5.59 to 8.5.66):
– multiframe alignment_error. Occurs when multiframe alignment fails
– frame alignment error. Occurs when multiframe alignment fails
– link configuration error. Occurs when there is wrong link configuration
– elastic buffer overflow. Occurs when bad RBD value is used
– elastic buffer match error. Occurs when the first non-/K/ doesn’t match the programmed data
– code synchronization error
– 8b/10b not-in-table decode error
– 8b/10b disparity error
– Field ALM_FROM_SHORTTEST in register ALM_SYSREF_PAP (8.5.67): Occurs when the short pattern
test fails.
• SerDes alarms
– Field ALM_SD_LOTDET in register ALM_SD_DET 8.5.5): Occurs when there are loss of signal detect
from SerDes lanes.
– Fields ALM_FIFOx_FLAGS in registers JESD_ALM_Lx (x = 0-7, 8.5.59 to 8.5.66):
– FIFO write error. Occurs if write request and FIFO is full.
– FIFO write full: Occurs if FIFO is full.
– FIFO read error. Occurs if read request and FIFO is empty.
– FIFO read empty: Occurs if FIFO is empty.
– Field ALM_SD0_PLL in register ALM_SYSREF_DET (8.5.6): Occurs if the PLL in the SerDes block 0
goes out of lock.
– Field ALM_SD1_PLL in register ALM_SYSREF_DET (8.5.6): Occurs if the PLL in the SerDes block 1
goes out of lock.
• SYSREF alarm
– Field ALM_SYSREF_ERR in register ALM_SYSREF_PAP (8.5.67): Occurs when the SYSREF is received
at an unexpected time. If too many of these occur it will cause the JESD to go into synchronization mode
again.
• DAC PLL alarm
– Field PLL_LOCK in register ALM_SYSREF_DET (8.5.6). This register field is asserted when the PLL is
unlocked. When used as an alarm output, a high signal indicates that the PLL is unlocked if the
ALM_OUT_POL bit in register RESET_CONFIG is set to 1.
• PAP alarm
– Field ALM_PAP in register ALM_SYSREF_PAP (8.5.67): Occurs when the average power is above the
threshold. While any alarm_pap is asserted the attenuation for the appropriate data path is applied.
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