DAC38RF82_17 Datasheet, PDF (92/140 Pages) Texas Instruments – Dual-Channel, Differential-Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface, On-Chip PLL and Wide-Band Interpolation

DAC38RF82, DAC38RF89
SLASEA6B – FEBRUARY 2017 – REVISED AUGUST 2017
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8.5.41 JESD Error Counter Register (address = 0x41) [reset = 0x0000]
Figure 92. JESD Error Counter Register (JESD_ERR_CNT)
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
x
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
1
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 88. JESD_ERR_CNT Field Descriptions
Bit Field
15:0 JESD_ERR_CNT
Type
R
Reset
0x0000
Description
This is the error count for the JESD link. This is a 16bit value
that is not cleared until the JESD synchronization is required or
errcnt_clr is programmed to '1'
8.5.42 JESD ID 1 Register (address = 0x46) [reset = 0x0044]
Figure 93. JESD ID 1 Register (JESD_ID1)
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
x
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
0
1
0
0
0
1
1
0
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
15:11
10:6
5:1
0
Field
LID0
LID1
LID2
Reserved
Table 89. JESD_ID1 Field Descriptions
Type
R/W
R/W
R/W
R/W
Reset
00000
00001
00010
0
Description
JESD ID for lane 0
JESD ID for lane 1
JESD ID for lane 2
Reserved
92
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