DAC38RF82_17 Datasheet, PDF (84/140 Pages) Texas Instruments – Dual-Channel, Differential-Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface, On-Chip PLL and Wide-Band Interpolation

DAC38RF82, DAC38RF89
SLASEA6B – FEBRUARY 2017 – REVISED AUGUST 2017
www.ti.com
8.5.27 SYSREF Use for Clock Divider Register (address = 0x24) [reset = 0x0010]
Figure 78. SYSREF Use for Clock Divder Register (SYSREF_CLKDIV)
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
0
0
1
0
0
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 74. SYSREF_CLKDIV Field Descriptions
Bit Field
15
Reserved
14:12 CDRVSER_SYSREF_DLY
11:7 Not used
6:4 SYSREF_MODE
3:2 SYSREF_DLY
1:0 Reserved
Type
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
000
00000
001
00
00
Description
Reserved
Programmable delay the SYSREF by N dacclk cycles to the
CDRV_SER clock dividers. By offsetting the clock to the
different multi-DUC blocks, clock mixing could potentially be
reduced.
Not used
Determines how SYSREF is used to sync the clock dividers in
the CDRV_SER block.
000 = Don’t use SYSREF pulse
001 = Use all SYSREF pulses
010 = Use only the next SYSREF pulse
011 = Skip one SYSREF pulse then use only the next one
100 = Skip one SYSREF pulse then use all pulses.
Delays the SYSREF into the CDRV_SER capture FF through 1
of 4 choices. This allows for extra delay in case the timing of the
clock or SYSREF path isn’t as good as we think.
Reserved
84
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