DAC38RF82_17 Datasheet, PDF (116/140 Pages) Texas Instruments – Dual-Channel, Differential-Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface, On-Chip PLL and Wide-Band Interpolation

DAC38RF82, DAC38RF89
SLASEA6B – FEBRUARY 2017 – REVISED AUGUST 2017
www.ti.com
8.5.77 Sleep Pin Control Register (address = 0x23) [reset = 0xFFFF]
These fields control the routing of the SLEEP signal to different blocks. Assertion means that the SLEEP signal
will be sent to the block. These bits do not override the SPI bits; just the SLEEP signal from the PAD.
Figure 128. Sleep Pin Control Register (SLEEP_CNTL)
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
0
0
1
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 124. SLEEP_CNTL Field Descriptions
Bit
15:10
9
8
7
6
5
4
3:2
1
0
Field
Reserved
CLKOUT_SLEEP
BG_SLEEP
TEMP_SLEEP
PLL_CP_SLEEP
PLL_SLEEP
CLK_RECV_SLEEP
Reserved
DACB_SLEEP
DACA_SLEEP
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
11111
1
1
1
1
1
1
11
1
1
Description
Reserved
Allows the output clock to sleep
Allows the band gap to sleep
Allows the temp sensor to sleep
Allows the PLL charge pump to sleep
Allows the PLL to sleep
Allows the clock receiver to sleep
Reserved
Allows DACB to sleep
Allows DACA to sleep
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