AFE7222 Datasheet, PDF (96/106 Pages) Texas Instruments – Analog Front End Wideband Mixed-Signal Transceiver

AFE7222
AFE7225
SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
www.ti.com
C<8> = Bit D2 of regster address 03F
C<7> = Bit D1 of regster address 03F
C<6> = Bit D0 of regster address 03F
C<5> = Bit D7 of regster address 040
C<4> = Bit D6 of regster address 040
C<3> = Bit D5 of regster address 040
C<2> = Bit D4 of regster address 040
C<1> = Bit D3 of regster address 040
C<0> = Bit D2 of regster address 040
For example, programming registers (Address 03F Data 29) and (Address 040 Data 34) replaces the
normal ADC data for both channels with the static binary code 101001001101.
DAC input format:
The DAC input format is also 2s complement similar to the ADC.
Full scale DAC current:
The full scale DAC current (IOUTFS) is set by the resistor (of value RBIASJ) on the BIASJ pin.
IOUTFS = 19.2/RBIASJ.
For RBIASJ=960Ω, IOUTFS = 20 mA
For the 12-bit input code (where CODE is the decimal representation of the DAC data input word in
straight offset binary format):
IOUTP = IOUTFS × CODE / 4096
IOUTN = IOUTFS × (4096 – CODE) / 4096
TX data input (CMOS mode):
The TX input data format is also DDR CMOS. The rising edge of the DAC_DCLKIN latches the Channel A
data inside the AFE7225/7222, and the falling edge latches the Channel B data. The clock rate of
DAC_DCLKIN is same as the input clock rate when interpolation is not set. When 2X interpolation is set, it
should be half the input clock rate, and when 4X interpolation is set, it should be one-fourth the input clock
rate.
DAC_DCLKIN
DACDATA <11:0>
BA B A B A B
Figure 11-2. TX CMOS Input Interface
Interpolation:
While interpolating by a factor of 2, the DAC_DCLKIN rate should be set to half of the input clock rate.
The 2X interpolation mode on the TX side can be set by the following register : Address 106, Data 05.
Powerdown modes:
The device has several powerdown modes which provide a tradeoff between power consumed and speed
of recovery from powerdown. The nature of the powerdown mode can be set through the registers. Also
the assertion of the powerdown can be done either through the PDN pin or through a register bit.
While using the PDN pin to control the powerdown state, the following are the register configurations (see
specifications table for recovery times)
Global powerdown mode through PDN pin : Set Address 207, Data 20, and control PDN pin to assert/
de-assert global powerdown mode. Most functions are shutdown.
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