AFE7222 Datasheet, PDF (37/106 Pages) Texas Instruments – Analog Front End Wideband Mixed-Signal Transceiver

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AFE7222
AFE7225
SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
RX_GLOBAL_SER_IF_SYNC – A rising edge on this is used as the sync source for RX . This is
applicable when RX_GLOBAL_SYNC_DIS is cleared, and RX_GLOBAL_SYNC_SRC specifies serial
interface bit to be the sync source for RX.
Register Name – CONFIG67 – Address 0x16B, Default = 0x00
<7> <6> <5>
<4>
<3>
<2>
RX_QMC_CORR_ RX_QMC_OFFSET_
ENA
ENA
<1>
RX_QMC_GAIN_PH_SYNC_
NEEDED
<0>
RX_QMC_OFF_SYNC_
NEEDED
RX_QMC_OFF_SYNC_NEEDED – Specifies if syncing is needed for RX QMC Offset Correction. If set,
QMC Offset values programmed into the serial interface registers are not applied to the QMC Offset
correction block until a Sync is applied.
RX_QMC_GAIN_PH_SYNC_NEEDED – Specifies if syncing is needed for RX QMC Gain Phase
Correction. If set, QMC gain and Phase values programmed into the serial interface registers are not
applied to the QMC Gain Phase correction block until a sync is applied.
RX_QMC_OFFSET_ENA – Enables RX QMC Offset Correction.
RX_QMC_CORR_ENA – Enable RX QMC Gain Phase Correction.
Register Name – CONFIG68 – Address 0x16C, Default = 0x00 (Synced)
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
RX_QMC_OFFSETA(12:5)
RX_QMC_OFFSETA(12:5) – Upper 8 bits of ADC A Offset Correction . The lower 5 bits are in CONFIG69
Register.
Register Name – CONFIG69 – Address 0x16D, Default = 0x00 (Synced)
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
RX_QMC_OFFSETA(4:0)
RX_QMC_GAINA(2:0)
RX_QMC_OFFSETA(4:0) – Lower 5 bits of ADC A Offset Correction .
RX_QMC_GAINA(2:0) – Lower 3 bits of the 11 bit QMC Gain word for ADC A. The upper 8 bits are in
CONFIG70 register.The full 11 bit RX_QMC_GAINA(10:0) word is formatted as UNSIGNED with a range
or 0 to 1.9990. The implied decimal point for the multiplication is between bits (9) and (10).
Register Name – CONFIG70 – Address 0x16E, Default = 0x00 (Synced)
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
RX_QMC_GAINA(10:3)
RX_QMC_GAINA(10:3) – Upper 8 bits if the 11 bit QMC Gain word for ADC A
Register Name – CONFIG71 – Address 0x16F, Default = 0x00 (Synced)
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
RX_QMC_OFFSETB(12:5)
RX_QMC_OFFSETB(12:5) – Upper 8 bits of ADC B Offset Correction . The lower 5 bits are in CONFIG72
Register.
Register Name – CONFIG72 – Address 0x170, Default = 0x00 (Synced)
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
RX_QMC_OFFSETB(4:0)
RX_QMC_GAINB(2:0)
RX_QMC_OFFSETB(4:0) – Lower 5 bits ofADC B Offset Correction .
RX_QMC_GAINB(2:0) – Lower 3 bits of the 11 bit QMC Gain word for ADC B. The upper 8 bits are in
CONFIG73 register.The full 11 bit RX_QMC_GAINB(10:0) word is formatted as UNSIGNED with a range
or 0 to 1.9990.
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REGISTER DESCRIPTIONS
37