AFE7222 Datasheet, PDF (22/106 Pages) Texas Instruments – Analog Front End Wideband Mixed-Signal Transceiver

AFE7222
AFE7225
SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
www.ti.com
Register Name – CONFIG1 – Address 0x104, Default = 0x10
<7>
<6>
<5>
<4>
<3>
<2>
MASK_2_AWAY_DET TX_CHB_8_IP_EN TX_CHA_8_IP_EN
<1>
<0>
TX_CHA_8_IP_EN – Enable the 8- sample mode FIFO mode for Channel A . The 8 samples written into
the regs 0x11F to 0x12E are repeatedly cycled through, and sent to the DAC A. This is a useful diagnostic
mode.
TX_CHB_8_IP_EN – Enable the 8- sample mode FIFO mode for Channel B . The 8 samples written into
the regs 0x12F to 0x13E are repeatedly cycled through, and sent to the DAC B.
MASK_2_AWAY_DET – Refer CONFIG58 for a description of the collision condition in the FIFO. Setting
the MASK_2_AWAY_DET prevents the 2-away condition from triggering collision detection. If collision
detection is enabled, and 2-away condition occurs, the output samples will be forced to DAC mid code,
unless MASK_2_AWAY_DET is set.
Register Name – CONFIG2 – Address 0x105, Default = 0x00
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
STORE_FIFO_PTRS
RX_TX_LPBK_SRC RX_TX_LPBK
STORE_FIFO_PTRS – When set , the FIFO Read and Write pointers are written into the register 0x141 at
the rate of the divided DAC_CLK. The pointers are no longer written to the serial interface regs when
Register readout is enabled.
RX_TX_LPBK – When this bit and RX_TX_LPBK_SRC are both set , the input to the TX signal chain is
tapped from the the final output of the RX signal chain. As is obvious, the ADC_CLK and DAC_CLK rates
should be the same when using this mode.
RX_TX_LPBK_SRC – When this bit and RX_TX_LPBK are both set , the input to the TX signal chain is
tapped from the the final output of the RX signal chain
The RX to TX loopback is shown below. The dotted arrows illustrate the loopback path.
Note that though the data going into the TX digital signal chain is looped back internally from the RX
Digital signal chain, it is still required to give an active DAC_DCLKIN in this mode because the Tx FIFO
requires it for proper data transfer.
INP_A_ADC
INN_A_ADC
INP_B_ADC
INN_B_ADC
12b
RX ADC A
12b
RX ADC B
12-bit ADC
Output
IOUTP_A_DAC
IOUTN_A_DAC
IOUTP_B_DAC
IOUTN_B_DAC
12b
TX DAC A
12b
TX DAC B
Figure 5-2. Loopback
12-bit DAC
Input
22
REGISTER DESCRIPTIONS
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