AFE7222 Datasheet, PDF (18/106 Pages) Texas Instruments – Analog Front End Wideband Mixed-Signal Transceiver

AFE7222
AFE7225
SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
www.ti.com
3.13 TIMING REQUIREMENTS FOR TRANSMIT PATH – LVDS AND CMOS MODES⁽¹⁾
Typical values are at 25°C, AVDD3_DAC = 3.0 V, AVDD3_AUX = 3.0 V, AVDD18_ADC = 1.8 V, DVDD18_CLK = 1.8 V,
DVDD18_DAC = 1.8 V, DVDD18 = 1.8 V, sine wave input clock, 1.5 V_pp clock amplitude, unless otherwise noted. Min and
max values are across the full temperature range T_MIN = -40°C to T_MAX = 85°C, AVDD3_DAC = 3.0 V, AVDD3_AUX = 3.0 V,
AVDD18_ADC = 1.8 V, DVDD18_CLK = 1.8 V, DVDD18_DAC = 1.8 V, DVDD18 = 1.7 V to 1.9 V
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
DAC Latency
Default Mode
16
clock
cycles
LVDS INPUT INTERFACE
t_su
Data setup time
Data valid⁽²⁾ to zero-crossing of DAC_DCLKINP
0.5
ns
t_h
Data hold time
Zero-crossing of DAC_DCLKINP to data becoming invalid ⁽²⁾
0.3
ns
CMOS INPUT INTERFACE
t_su
Data setup time
Data valid to cross-over of DAC_DCLKIN ⁽³⁾
0.3
ns
t_h
Data hold time
Cross-over of DAC_DCLKIN to data becoming invalid ⁽³⁾
0.5
ns
(1) Timing parameters are ensured by design and characterization and not tested in production.
(2) Data valid refers to LOGIC HIGH of +100 mV and LOGIC LOW of -100 mV.
(3) Data valid refers to LOGIC HIGH of 1.26 V and LOGIC LOW of 0.54 V.
18
ELECTRICAL SPECIFICATIONS
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