TM4C129DNCPDT Datasheet, PDF (932/1946 Pages) Texas Instruments – Tiva Microcontroller

External Peripheral Interface (EPI)
Register 39: EPI Host-Bus 16 Timing Extension (EPIHB16TIME), offset 0x310
Important: The MODE field in the EPICFG register determines which configuration is enabled.
For EPIHB16TIME to be valid, the MODE field must be 0x3.
EPI Host-Bus 16 Timing Extension (EPIHB16TIME)
Base 0x400D.0000
Offset 0x310
Type RW, reset 0x0002.2000
31
30
29
28
27
26
25
24
23
reserved
IRDYDLY
Type RO
RO
RO
RO
RO
RO
RW
RW
RO
Reset
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
reserved
CAPWIDTH
reserved
Type RO
RO
RW
RW
RO
RO
RO
RO
RO
Reset
0
0
1
0
0
0
0
0
0
22
21
20
19
18
17
16
reserved
PSRAMSZ
RO
RO
RO
RO
RW
RW
RW
0
0
0
0
0
1
0
6
5
4
3
2
1
0
WRWSM
reserved
RDWSM
RO
RO
RW
RO
RO
RO
RW
0
0
0
0
0
0
0
Bit/Field
31:26
25:24
Name
reserved
IRDYDLY
Type
RO
RW
Reset
0x00
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
CS0n Input Ready Delay
Value Description
0 reserved
1 Stall begins one EPI clocks past iRDY low being sampled on
the rising edge of EPIO clock.
2 Stall begins two EPI clocks past iRDY low being sampled on
the rising edge of EPIO clock.
3 Stall begins three EPI clocks past iRDY low being sampled on
the rising edge of EPIO clock.
23:19
18:16
reserved
PSRAMSZ
RO
0x000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RW
0x2
PSRAM Row Size
Defines the row size for the PSRAM controlled by CS0n
Value Description
0x0 No row size limitation
0x1 128 B
0x2 256 B
0x3 512 B
0x4 1024 B
0x5 2048 B
0x6 4096 B
0x7 8192 B
932
June 18, 2014
Texas Instruments-Production Data