TM4C129DNCPDT Datasheet, PDF (30/1946 Pages) Texas Instruments – Tiva Microcontroller

Table of Contents
Register 116: Analog Comparator Sleep Mode Clock Gating Control (SCGCACMP), offset 0x73C .......... 424
Register 117: Pulse Width Modulator Sleep Mode Clock Gating Control (SCGCPWM), offset 0x740 ........ 425
Register 118: Quadrature Encoder Interface Sleep Mode Clock Gating Control (SCGCQEI), offset
0x744 ........................................................................................................................... 426
Register 119: EEPROM Sleep Mode Clock Gating Control (SCGCEEPROM), offset 0x758 ..................... 427
Register 120: CRC and Cryptographic Modules Sleep Mode Clock Gating Control (SCGCCCM), offset
0x774 ........................................................................................................................... 428
Register 121: Ethernet MAC Sleep Mode Clock Gating Control (SCGCEMAC), offset 0x79C .................. 429
Register 122: Watchdog Timer Deep-Sleep Mode Clock Gating Control (DCGCWD), offset 0x800 .......... 430
Register 123: 16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating Control (DCGCTIMER),
offset 0x804 .................................................................................................................. 431
Register 124: General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control (DCGCGPIO), offset
0x808 ........................................................................................................................... 433
Register 125: Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control (DCGCDMA), offset
0x80C ........................................................................................................................... 436
Register 126: EPI Deep-Sleep Mode Clock Gating Control (DCGCEPI), offset 0x810 ............................. 437
Register 127: Hibernation Deep-Sleep Mode Clock Gating Control (DCGCHIB), offset 0x814 .................. 438
Register 128: Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control
(DCGCUART), offset 0x818 ............................................................................................ 439
Register 129: Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control (DCGCSSI), offset
0x81C ........................................................................................................................... 441
Register 130: Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control (DCGCI2C), offset
0x820 ........................................................................................................................... 442
Register 131: Universal Serial Bus Deep-Sleep Mode Clock Gating Control (DCGCUSB), offset
0x828 ........................................................................................................................... 444
Register 132: Controller Area Network Deep-Sleep Mode Clock Gating Control (DCGCCAN), offset
0x834 ........................................................................................................................... 445
Register 133: Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control (DCGCADC), offset
0x838 ........................................................................................................................... 446
Register 134: Analog Comparator Deep-Sleep Mode Clock Gating Control (DCGCACMP), offset
0x83C ........................................................................................................................... 447
Register 135: Pulse Width Modulator Deep-Sleep Mode Clock Gating Control (DCGCPWM), offset
0x840 ........................................................................................................................... 448
Register 136: Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control (DCGCQEI), offset
0x844 ........................................................................................................................... 449
Register 137: EEPROM Deep-Sleep Mode Clock Gating Control (DCGCEEPROM), offset 0x858 ........... 450
Register 138: CRC and Cryptographic Modules Deep-Sleep Mode Clock Gating Control (DCGCCCM),
offset 0x874 .................................................................................................................. 451
Register 139: Ethernet MAC Deep-Sleep Mode Clock Gating Control (DCGCEMAC), offset 0x89C ......... 452
Register 140: Watchdog Timer Power Control (PCWD), offset 0x900 ..................................................... 453
Register 141: 16/32-Bit General-Purpose Timer Power Control (PCTIMER), offset 0x904 ....................... 455
Register 142: General-Purpose Input/Output Power Control (PCGPIO), offset 0x908 .............................. 458
Register 143: Micro Direct Memory Access Power Control (PCDMA), offset 0x90C ................................ 463
Register 144: External Peripheral Interface Power Control (PCEPI), offset 0x910 ................................... 465
Register 145: Hibernation Power Control (PCHIB), offset 0x914 ............................................................ 467
Register 146: Universal Asynchronous Receiver/Transmitter Power Control (PCUART), offset 0x918 ...... 469
Register 147: Synchronous Serial Interface Power Control (PCSSI), offset 0x91C .................................. 472
Register 148: Inter-Integrated Circuit Power Control (PCI2C), offset 0x920 ............................................ 474
Register 149: Universal Serial Bus Power Control (PCUSB), offset 0x928 .............................................. 478
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June 18, 2014
Texas Instruments-Production Data