TM4C129DNCPDT Datasheet, PDF (605/1946 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129DNCPDT Microcontroller
Figure 8-2. Flash Memory Configuration
0x0F.FFFC
0x0F.FFF8
0x0F.FFF4
0x0F.FFF0
0x0F.FFEC 0x0F.FFE8 0x0F.FFE4 0x0F.FFE0
8 KB Sector31-1 Bank 3
0x08.401C
0x08.3FFC
0x08.001C
0x07.FFFC
0x08.4018
0x08.4014
0x08.3FF8 0x08.3FF4
8 KB Sector 0 Bank 3
0x08.0018
0x08.0014
256 KB Bank 3: 128-bit output
0x07.FFF8 0x07.FFF4
0x08.4010
0x08.3FF0
0x08.0010
0x07.FFF0
0x08.400C
0x08.3FEC
0x08.000C
0x07.FFEC
8 KB Sector31-1 Bank 2
0x08.4008
0x08.4004
0x08.3FE8 0x08.3FE4
8 KB Sector 0 Bank 2
0x08.0008
0x08.0004
256 KB Bank 2: 128-bit output
0x07.FFE8 0x07.FFE4
0x08.4000
0x08.3FE0
0x08.0000
0x07.FFE0
512 KB
High Region
16 KB
1 MB Flash
8 KB Sector31-1 Bank 1
0x00.401C
0x00.3FFC
0x00.001C
0x00.4018
0x00.4014
0x00.3FF8 0x00.3FF4
8 KB Sector 0 Bank 1
0x00.0018
0x00.0014
256 KB Bank 1: 128-bit output
0x00.4010
0x00.3FF0
0x00.0010
0x00.400C
0x00.3FEC
0x00.000C
8 KB Sector31-1 Bank 0
0x00.4008
0x00.4004
0x00.3FE8 0x00.3FE4
8 KB Sector 0 Bank 0
0x00.0008
0x00.0004
256 KB Bank 0: 128-bit output
0x00.4000
0x00.3FE0
0x00.0000
512 KB
Low Region
16 KB
8.2.3.1
The interleaved memory prefetchs 256 bits at a time. The prefetch buffers allow the maximum
performance of a 120 MHz CPU speed to be maintained with linear code or loops that fit within the
prefetch buffer. It is recommended that code be compiled with switches set to eliminate "literals" as
much as possible as a literal causes a flash access for that word and a stall for the wait states. Most
compilers support transforming literals into "in-line" code, which executes faster in a system where
the memory subsystem is slower than the CPU.
Because the memory is two-way interleaved and each bank individually is an 8-KB sector, when
the user erases a sector, using the ERASE bits in the Flash Memory Control (FMC) register, it is
a 16 KB erase. Erasing a block causes the entire contents of the block to be reset to all 1s.
Flash Configuration
Depending on the CPU frequency, the application must program the Flash clock high time (FBCHT),
Flash Bank Clock Edge (FBCE) and Flash wait states (FWS) in the Memory Timing Parameter
Register 0 for Main Flash and EEPROM (MEMTIM0), System Control Module offset 0x0C0. The
following table details the bit field values that are required for the given CPU frequency ranges.
Table 8-1. MEMTIM0 Register Configuration versus Frequency
CPU Frequency range (f) Time Period Range (t) in ns Flash Bank Clock
in MHz
High Time (FBCHT)
16
62.5
0x0
16 < f ≤ 40
62.5 > t ≥ 25
0x2
40 < f ≤60
25 > t ≥ 16.67
0x3
60< f ≤80
16.67 > t ≥ 12.5
0x4
80 < f ≤100
12.5 > t ≥ 10
0x5
Flash Bank
Clock Edge
(FBCE)
1
0
0
0
0
Flash Wait States
(FWS)
0x0
0x1
0x2
0x3
0x4
June 18, 2014
605
Texas Instruments-Production Data