TM4C129DNCPDT Datasheet, PDF (1553/1946 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129DNCPDT Microcontroller
if the corresponding RI bit is enabled in the EMACDMAIM register. This counter gets disabled
before it runs out if a frame is transferred to memory and the RI bit is set because it is enabled for
that descriptor.
23.3.3.9
DMA Bus Error
If an internal bus error occurs during a DMA transfer, the fatal bus error (FBI) interrupt is set in the
EMACDMARIS register and the Access Error status (AE) bit field in the EMACDMARIS register
indicates the type of error that caused the bus error. The DMA controller can resume operation only
after soft resetting the Ethernet MAC and the re-initializing the DMA.
23.3.4
TX/RX Controller
The TX/RX Controller consists of a FIFO memory which buffers and regulates the frames between
the system memory and the MAC. It also controls the data transferred between clock domains. Both
the transmit and receive data paths are 32-bits wide. The TX FIFO and RX FIFO are each 2 KB in
depth.
At reset, the TX/RX Controller is configured and ready to manage data flow to and from the DMA
to the MAC. Note that the DMA and MAC must be initialized by the application out of reset.
23.3.4.1
Transmit (TX) Control Path
The DMA controller is used for all Ethernet transmissions. The Ethernet frames are read from
memory and transferred to the TX FIFO by the DMA. When the MAC is available, the frame is
transferred from the FIFO. When the end-of-frame (EOF) is transferred, the MAC notifies the DMA
the status of the transmission.
The TX FIFO has a depth of 2 KB. The FIFO fill level has the capability of triggering the DMA to
initiate a burst transfer. The DMA also transfers start-of-frame (SOF), end-of-frame (EOF), CRC
and pad-insertion information to the TX/RX Controller so that this information can be passed to the
MAC when it is ready for transmission from the TX FIFO.
Data can be transmitted to the MAC in threshold mode or store-and-forward mode. If the TTC field
is configured in the Ethernet MAC DMA Operation Mode (EMACDMAOPMODE) register at offset
0xC18 and the TSF bit in the same register is 0x0, then the TX Controller is operating in threshold
mode. In this mode, the data is transferred to the MAC when the number of bytes in the FIFO crossed
the value configured in the TTC bit field or when the end-of-frame is written before the threshold is
crossed. In store-and forward mode, the TTC bit field is configured and the TSF bit is set. Data is
transferred to the MAC only when one or more of the following conditions are true:
■ A complete frame is stored in the FIFO
■ The TX FIFO becomes almost full
■ The TX FIFO does not have space to accommodate the requested burst length
With these conditions, the TX Controller continues store-and-forward mode even if the Ethernet
frame length is bigger than the TX FIFO size.
The TX FIFO can be flushed of all contents by setting the FTF bit in the EMACDMAOPMODE
register. This bit is self-clearing and initializes the FIFO pointers to the default state. If the FTF bit
is set during a frame transfer from the TX Controller to the MAC, then the TX Controller stops further
transfer. Early termination of the transfer causes a underflow event and this status is communicated
to the DMA.
June 18, 2014
Texas Instruments-Production Data
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