TM4C129DNCPDT Datasheet, PDF (1307/1946 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129DNCPDT Microcontroller
Bit/Field
7
6
5
4
3
Name
LBE
reserved
HSE
EOT
SMART
Type
RW
RO
RW
RW
RW
Reset
0
Description
UART Loop Back Enable
Value Description
0 Normal operation.
1 The UnTx path is fed through the UnRx path.
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
High-Speed Enable
Value Description
0 The UART is clocked using the system clock divided by 16.
1 The UART is clocked using the system clock divided by 8.
Note:
System clock used is also dependent on the baud-rate divisor
configuration (see page 1301) and page 1302).
The state of this bit has no effect on clock generation in ISO
7816 smart card mode (the SMART bit is set).
0
End of Transmission
This bit determines the behavior of the TXRIS bit in the UARTRIS
register.
Value Description
0 The TXRIS bit is set when the transmit FIFO condition specified
in UARTIFLS is met.
1 The TXRIS bit is set only after all transmitted data, including
stop bits, have cleared the serializer.
0
ISO 7816 Smart Card Support
Value Description
0 Normal operation.
1 The UART operates in Smart Card mode.
The application must ensure that it sets 8-bit word length (WLEN set to
0x3) and even parity (PEN set to 1, EPS set to 1, SPS set to 0) in
UARTLCRH when using ISO 7816 mode.
In this mode, the value of the STP2 bit in UARTLCRH is ignored and
the number of stop bits is forced to 2. Note that the UART does not
support automatic retransmission on parity errors. If a parity error is
detected on transmission, all further transmit operations are aborted
and software must handle retransmission of the affected byte or
message.
June 18, 2014
Texas Instruments-Production Data
1307