TM4C129DNCPDT Datasheet, PDF (779/1946 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129DNCPDT Microcontroller
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514
The GPIOPDR register is the pull-down control register. When a bit is set, a weak pull-down resistor
on the corresponding GPIO signal is enabled. Setting a bit in GPIOPDR automatically clears the
corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 777).
Important: The table below shows special consideration GPIO pins. Most GPIO pins are configured
as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
GPIOPUR=0, and GPIOPCTL=0). Special consideration pins may be programed to a
non-GPIO function or may have special commit controls out of reset. In addition, a
Power-On-Reset (POR) returns these GPIO to their original special consideration state.
Table 10-10. GPIO Pins With Special Considerations
GPIO Pins Default Reset GPIOAFSEL GPIODEN GPIOPDR GPIOPUR GPIOPCTL GPIOCR
State
PC[3:0]
JTAG/SWD
1
PD[7]
GPIO^a
0
PE[7]
GPIO^a
0
1
0
1
0x1
0
0
0
0
0x0
0
0
0
0
0x0
0
a. This pin is configured as a GPIO by default but is locked and can only be reprogrammed by unlocking the
pin in the GPIOLOCK register and uncommitting it by setting the GPIOCR register.
The GPIO commit control registers provide a layer of protection against accidental
programming of critical hardware signals including the GPIO pins that can function as
JTAG/SWD signals and the NMI signal. The commit control process must be followed
for these pins, even if they are programmed as alternate functions other than JTAG/SWD
or NMI; see “Commit Control” on page 753.
Note:
If the device fails initialization during reset, the hardware toggles the TDO output
as an indication of failure. Thus, during board layout, designers should not
designate the TDO pin as a GPIO in sensitive applications where the possibility
of toggling could affect the design.
Note:
The GPIO commit control registers provide a layer of protection against accidental
programming of critical hardware peripherals. Protection is provided for the GPIO pins that
can be used as the four JTAG/SWD pins and the NMI pin (see “Signal Tables” on page 1825
for pin numbers). Writes to protected bits of the GPIO Alternate Function Select
(GPIOAFSEL) register (see page 771), GPIO Pull Up Select (GPIOPUR) register (see
page 777), GPIO Pull-Down Select (GPIOPDR) register (see page 779), and GPIO Digital
Enable (GPIODEN) register (see page 782) are not committed to storage unless the GPIO
Lock (GPIOLOCK) register (see page 784) has been unlocked and the appropriate bits of
the GPIO Commit (GPIOCR) register (see page 785) have been set.
June 18, 2014
779
Texas Instruments-Production Data