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TM4C129DNCPDT Datasheet, PDF (56/1946 Pages) Texas Instruments – Tiva Microcontroller
Architectural Overview
1.2
In addition, Tiva™ C Series microcontrollers offer the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure, and a large user community. Additionally,
these microcontrollers use ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory
requirements and, thereby, cost. Finally, the TM4C129DNCPDT microcontroller is code-compatible
to all members of the extensive Tiva™ C Series, providing flexibility to fit precise needs.
Texas Instruments offers a complete solution to get to market quickly, with evaluation and
development boards, white papers and application notes, an easy-to-use peripheral driver library,
and a strong support, sales, and distributor network.
TM4C129DNCPDT Microcontroller Overview
The TM4C129DNCPDT microcontroller combines complex integration and high performance with
the features shown in Table 1-1.
Table 1-1. TM4C129DNCPDT Microcontroller Features
Feature
Performance
Core
Performance
Flash
System SRAM
EEPROM
Internal ROM
External Peripheral Interface (EPI)
Security
Cyclical Redundancy Check (CRC) Hardware
Advanced Encryption Standard (AES)
Data Encryption Standard (DES)
Hardware Accelerated Hash (SHA/MD5)
Tamper
Communication Interfaces
Universal Asynchronous Receivers/Transmitter
(UART)
Quad Synchronous Serial Interface (QSSI)
Inter-Integrated Circuit (I2C)
Controller Area Network (CAN)
Ethernet MAC
Universal Serial Bus (USB)
System Integration
Micro Direct Memory Access (µDMA)
General-Purpose Timer (GPTM)
Watchdog Timer (WDT)
Description
ARM Cortex-M4F processor core
120-MHz operation; 150 DMIPS performance
1024 KB Flash memory
256 KB single-cycle System SRAM
6KB of EEPROM
Internal ROM loaded with TivaWare™ for C Series software
8-/16-/32- bit dedicated interface for peripherals and memory
16-/32-bit Hash function that supports four CRC forms
Hardware accelerated data encryption and decryption based on 128-,
192-, and 256-bit keys
Block cipher implementation with 168-bit effective key length
Advanced hash engine that supports SHA-1, SHA-2 or MD5 Hash
computation
Support for four tamper inputs and configurable tamper event response
Eight UARTs
Four SSI modules with Bi-, Quad- and advanced SSI support
Ten I2C modules with four transmission speeds including high-speed
mode
Two CAN 2.0 A/B controllers
10/100 Ethernet MAC with Media Independent Interface (MII) and
Reduced MII (RMII)
USB 2.0 OTG/Host/Device with ULPI interface option and Link Power
Management (LPM) support
ARM® PrimeCell® 32-channel configurable μDMA controller
Eight 16/32-bit GPTM blocks
Two watchdog timers
56
June 18, 2014
Texas Instruments-Production Data