MSP432P401R_16 Datasheet, PDF (90/200 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP432P401R, MSP432P401M
SLAS826E – MARCH 2015 – REVISED JULY 2016
www.ti.com
6 Detailed Description
6.1 Overview
The MSP432P401x microcontroller is an ideal combination of the TI MSP430 low-power DNA, advance
mixed-signal features, and the processing capabilities of the ARM 32-bit Cortex-M4 RISC engine. The
microcontrollers ship with bundled driver libraries and are compatible with standard components of the
ARM ecosystem.
6.2 Processor and Execution Features
The Cortex-M4 processor provides a high-performance low-cost platform that meets system requirements
of minimal memory implementation, reduced pin count, and low power consumption, while delivering
outstanding computational performance and exceptional system response to interrupts. The Thumb^®-2
mixed 16- and 32-bit instruction set of the processor delivers the high performance that is expected of a
32-bit ARM core in a compact memory size usually associated with 8- and 16-bit devices (typically in the
range of a few kilobytes of memory needed for microcontroller-class applications).
In the MSP432P401x MCUs, the Cortex-M4 processor can run up to 48 MHz, delivering high performance
for the targeted class of applications, while at the same time maintaining ultra-low active power
consumption.
6.2.1 Floating-Point Unit
The Cortex-M4 processor on the MSP432P401x MCUs includes a tightly coupled floating-point unit (FPU).
The FPU is an IEEE 754 compliant single precision floating point module supporting add, subtract,
multiply, divide, accumulate, and square-root operations. It also provides conversion between fixed-point
and floating-point data formats and floating point constant instructions.
6.2.2 Memory Protection Unit
The Cortex-M4 processor on the MSP432P401x MCUs includes a tightly coupled memory protection unit
(MPU) that supports up to eight protection regions. Applications can use the MPU to enforce memory
privilege rules that isolate processes from each other or enforce memory access rules. These features are
typically required for operating system handling purposes.
6.2.3 Nested Vectored Interrupt Controller (NVIC)
The NVIC supports up to 64 interrupts with eight levels of interrupt priority. The Cortex-M4 NVIC
architecture allows for low latency, efficient interrupt and event handling, and seamless integration to
device-level power-control strategies.
6.2.4 SysTick
The Cortex-M4 includes an integrated system timer, SysTick, which provides a simple, 24-bit, clear-on-
write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in
several different ways, and it is typically deployed either for operating system related purposes or as a
general-purpose alarm mechanism.
6.2.5 Debug and Trace Features
The Cortex-M4 processor implements a complete hardware debug solution and provides high system
visibility of the processor and memory through either a traditional 4-pin JTAG port or a 2-pin Serial Wire
Debug (SWD) port, which is ideal for microcontrollers and other small-package devices. The SWJ-DP
interface combines the SWD and JTAG debug ports into one module, which allows a seamless switch
between the 2-pin and 4-pin modes of operation, depending on application needs.
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Detailed Description
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