MSP432P401R_16 Datasheet, PDF (31/200 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP432P401R, MSP432P401M
SLAS826E – MARCH 2015 – REVISED JULY 2016
5.8 Operating Mode Execution Frequency vs Flash Wait-State Requirements
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
NUMBER OF
FLASH WAIT
STATES
FLASH READ
MODE
MAXIMUM SUPPORTED MCLK FREQUENCY^{(1) (2)}
AM_LDO_VCORE0,
AM_DCDC_VCORE0
AM_LDO_VCORE1,
AM_DCDC_VCORE1
UNIT
f_{MAX_NRM_FLWAIT0}
0
Normal read
mode
16
24
MHz
f_{MAX_NRM_FLWAIT1}
1
Normal read
mode
24
48
MHz
f_{MAX_ORM_FLWAIT0}
0
Other read
modes ⁽³⁾
8
12
MHz
f_{MAX_ORM_FLWAIT1}
1
Other read
modes ⁽³⁾
16
24
MHz
f_{MAX_ORM_FLWAIT2}
2
Other read
modes ⁽³⁾
24
36
MHz
f_{MAX_ORM_FLWAIT3}
3
Other read
modes ⁽³⁾
24
48
MHz
(1) Violation of the maximum frequency limitation for a given wait-state configuration results in nondeterministic data or instruction fetches
from the flash memory.
(2) In low-frequency active modes, the flash can always be accessed with zero wait states, because the maximum MCLK frequency is
limited to 128 kHz.
(3) Other read modes refers to Read Margin 0, Read Margin 1, Program Verify, and Erase Verify.
5.9 Current Consumption During Device Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) ^{(1) (2) (3)}
I_RESET
PARAMETER
Current during device reset
V_CC
2.2 V
3.0 V
MIN TYP MAX UNIT
510
µA
600 850
(1) Device held in reset through RSTn/NMI pin.
(2) Current measured into V_CC.
(3) All other input pins tied to 0 V or V_CC. Outputs do not source or sync any current.
5.10 Current Consumption in LDO-Based Active Modes – Dhrystone 2.1 Program
over recommended operating free-air temperature (unless otherwise noted)^{(1) (2) (3) (4) (5)}
PARAMETER
I_{AM_LDO_VCORE0,Flash(6)} ^{(7) (8)}
I_{AM_LDO_VCORE1,Flash(6)} ^{(7) (8)}
I_{AM_LDO_VCORE0,SRAM} ⁽⁹⁾
I_{AM_LDO_VCORE1,SRAM} ⁽⁹⁾
EXECUTION
MEMORY
Flash
Flash
SRAM
SRAM
V_CC
3.0 V
3.0 V
3.0 V
3.0 V
MCLK = 1 MHz MCLK = 8 MHz
TYP MAX TYP MAX
490 625 1500 1700
510 685 1650 1900
435 565 1070 1240
450 620 1160 1370
MCLK =
16 MHz
TYP MAX
2650 2950
2970 3300
1800 2010
1980 2250
MCLK =
24 MHz
TYP MAX
3580 3900
4260 4700
2530 2800
2800 3120
MCLK =
32 MHz
TYP MAX
5300 5800
3650 4020
MCLK =
40 MHz
TYP MAX
6500 7100
4470 4900
(1) MCLK sourced by DCO.
(2) Current measured into V_CC.
(3) All other input pins tied to 0 V or V_CC. Outputs do not source or sync any current.
(4) All SRAM banks kept active.
(5) All peripherals are inactive.
(6) Device executing the Dhrystone 2.1 program. Code execution from flash. Stack and data in SRAM.
(7) Flash configured to minimum wait states required to support operation at given frequency and core voltage level.
(8) Flash instruction and data buffers are enabled (BUFI = BUFD = 1).
(9) Device executing the Dhrystone 2.1 program. Code execution from SRAM. Stack and data in SRAM.
MCLK =
48 MHz
UNIT
TYP MAX
µA
7700 8400 µA
µA
5280 5760 µA
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Specifications
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