MSP432P401R_16 Datasheet, PDF (83/200 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP432P401R, MSP432P401M
SLAS826E – MARCH 2015 – REVISED JULY 2016
Table 5-39 lists the characteristics of the eUSCI in SPI slave mode.
Table 5-39. eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾
PARAMETER
t_STE,LEAD STE lead time, STE active to clock
TEST CONDITIONS
V_CC
1.62 V
3.7 V
MIN MAX UNIT
45
ns
20
t_STE,LAG STE lag time, Last clock to STE inactive
1.62 V
1
ns
3.7 V
1
t_STE,ACC STE access time, STE active to SOMI data out
1.62 V
3.7 V
25
ns
15
t_STE,DIS
STE disable time, STE inactive to SOMI high
impedance
1.62 V
3.7 V
18
ns
14
t_SU,SI
SIMO input data setup time
1.62 V
3
ns
3.7 V
2
t_HD,SI
SIMO input data hold time
1.62 V
0
ns
3.7 V
0
t_VALID,SO SOMI output data valid time⁽²⁾
UCLK edge to SOMI valid,
C_L = 20 pF
1.62 V
3.7 V
35
ns
18
t_HD,SO
SOMI output data hold time⁽³⁾
C_L = 20 pF
1.62 V
10
ns
3.7 V
6
(1) f_UCxCLK = 1/2t_LO/HI with tL_O/HI ≥ max(t_{VALID,MO(Master)} + t_SU,SI(eUSCI), t_{SU,MI(Master)} + t_{VALID,SO(eUSCI)}).
For the master parameters t_{SU,MI(Master)} and t_{VALID,MO(Master)} see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-71 and Figure 5-72.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-71
and Figure 5-72.
UCMODEx = 01
STE
UCMODEx = 10
CKPL = 0
UCLK
CKPL = 1
SIMO
t
STE,LEAD
1/f
UCxCLK
t
LOW/HIGH
t
LOW/HIGH
t
STE,LAG
t
SU,SI
t
HD,SI
SOMI
t
STE,ACC
t
HD,SO
t
VALID,SO
t
STE,DIS
Figure 5-71. SPI Slave Mode, CKPH = 0
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Specifications
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