MSP432P401R_16 Datasheet, PDF (40/200 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP432P401R, MSP432P401M
SLAS826E – MARCH 2015 – REVISED JULY 2016
www.ti.com
5.23 Current Consumption of Digital Peripherals
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾
PARAMETER
TEST CONDITIONS
TYP
I_{TIMER_A}
Timer_A configured as PWM timer with 50% duty cycle
5
I_TIMER32
Timer32 enabled
3.5
I_UART
eUSCI_A configured in UART mode
6.5
I_SPI
eUSCI_A configured in SPI master mode
5
I_I2C
eUSCI_B configured in I²C master mode
5
I_{WDT_A}
WDT_A configured in interval timer mode
6
I_{RTC_C}
RTC_C enabled and sourced from 32-kHz LFXT
100
I_AES256
AES256 active
19
I_CRC32
CRC32 active
2
(1) Measured with VCORE = 1.2 V
MAX
UNIT
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
nA
µA/MHz
µA/MHz
5.24 Thermal Resistance Characteristics
Rθ_JA
Rθ_JC(TOP)
Rθ_JB
Ψ_JB
Ψ_JT
Rθ_JC(BOTTOM)
Rθ_JA
Rθ_JC(TOP)
Rθ_JB
Ψ_JB
Ψ_JT
Rθ_JC(BOTTOM)
Rθ_JA
Rθ_JC(TOP)
Rθ_JB
Ψ_JB
Ψ_JT
Rθ_JC(BOTTOM)
THERMAL METRICS⁽¹⁾
Junction-to-ambient thermal resistance, still air⁽³⁾
Junction-to-case (top) thermal resistance⁽⁴⁾
Junction-to-board thermal resistance⁽⁵⁾
Junction-to-board thermal characterization parameter
Junction-to-top thermal characterization parameter
Junction-to-case (bottom) thermal resistance⁽⁶⁾
Junction-to-ambient thermal resistance, still air⁽³⁾
Junction-to-case (top) thermal resistance⁽⁴⁾
Junction-to-board thermal resistance⁽⁵⁾
Junction-to-board thermal characterization parameter
Junction-to-top thermal characterization parameter
Junction-to-case (bottom) thermal resistance⁽⁶⁾
Junction-to-ambient thermal resistance, still air⁽³⁾
Junction-to-case (top) thermal resistance⁽⁴⁾
Junction-to-board thermal resistance⁽⁵⁾
Junction-to-board thermal characterization parameter
Junction-to-top thermal characterization parameter
Junction-to-case (bottom) thermal resistance⁽⁶⁾
PACKAGE
LQFP-100 (PZ)
NFBGA-80 (ZXH)
VQFN-64 (RGC)
VALUE ⁽²⁾
50.9
9.7
27.2
26.9
0.2
N/A
58.1
26.1
22.6
22.0
0.5
N/A
29.4
14.8
8.3
8.2
0.2
1.0
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) N/A = not applicable
(3) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(4) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(5) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
40
Specifications
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