MSP432P401R_16 Datasheet, PDF(132/200 Page) Texas Instruments

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MSP432P401R_16 Datasheet, PDF (132/200 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP432P401R, MSP432P401M

SLAS826E â MARCH 2015 â REVISED JULY 2016

www.ti.com

6.9.7 Watchdog Timer (WDT_A)

The primary function of the WDT_A module is to perform a controlled system restart if a software problem

occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not

needed in an application, the module can be configured as an interval timer and can generate interrupts at

selected time intervals.

CAUTION

The WDT must be set to interval mode before transitioning into the LPM3 or

LPM3.5 modes of operation. This allows the WDT event to wake the device

and return it to active modes of operation. Using the WDT in watchdog mode

may result in nondeterministic behavior due to the generated reset.

The watchdog can generate a reset on either a time-out or a password violation. This reset can be

configured to generate either a Hard Reset or a Soft Reset into the system. See the MSP432P4xx Family

Technical Reference Manual for more details. The WDT should typically be configured to generate a Hard

reset into the system. A Soft reset resets the CPU but leaves the rest of the system and peripherals

unaffected. As a result, if the WDT is configured to generate a Soft reset, the application should assume

responsibility for the fact that a Soft reset can corrupt an ongoing transaction from the CPU into the

system.

Table 6-50 lists the clocks that can be selected as the source for the WDT_A module.

Table 6-50. WDT_A Clocks

WDTSSEL

NORMAL OPERATION

(WATCHDOG AND INTERVAL TIMER MODE)

SMCLK

ACLK

VLOCLK

BCLK

6.9.8 ADC14

The ADC14 module supports 14-bit analog-to-digital conversions up to 1 Msps sampling rate with

differential and single-ended inputs. The module implements a 14-bit SAR core, sample and hold circuit,

reference generator and a conversion result buffer. The window comparators with a lower and upper limit

allow CPU independent result monitoring through different window comparator interrupt flags.

132 Detailed Description

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