TLC5951 Datasheet, PDF (9/46 Pages) Texas Instruments – 24-Channel, 12-Bit PWM LED Driver with 7-Bit Dot Correction and 3-Group, 8-Bit Global Brightness Control

TLC5951
www.ti.com
NAME
TERMINAL
NO.
DAP
RHA
GSSIN
1
26
GSSCK
2
27
GSLAT
3
28
GSSOUT
19
5
DCSIN
38
25
DCSCK
37
24
DCSOUT
20
6
GSCKR
5
30
GSCKG
4
29
GSCKB
6
31
XBLNK
36
23
IREF
34
21
OUTR0-
OUTR7
8, 11, 14, 2, 9, 12, 15,
17, 22, 25, 18, 33, 36,
28, 31
39
TERMINAL FUNCTIONS
SBVS127B – MARCH 2009 – REVISED DECEMBER 2009
I/O
DESCRIPTION
Serial data input for the 288-bit common shift register for grayscale (GS), dot
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correction (DC), global brightness control (BC), and function control (FC) data.
GSSIN is connected to the LSB of the 288-bit common shift register. This pin is
internally pulled to GND with a 500-kΩ resistor.
Serial data shift clock for the 288-bit common shift register for GS/DC/BC/FC data.
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Data present on GSSIN are shifted into the LSB of the shift register with the rising
edge of GSSCK. Data in the shift register are shifted toward the MSB at each
rising edge of GSSCK. The MSB data of the shift register appear on GSSOUT.
Data in the 288-bit common shift register are copied to the GS data latch or to the
DC/BC/FC data latch at the rising edge of GSLAT. The level of GSLAT at the last
GSSCK before the GSLAT rising edge determines which of the two latches the
data are transferred into. When GSLAT is low at the last GSSCK rising edge, all
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288 bits in the common shift register are copied to the GS data latch. When
GSLAT is high at the last GSSCK rising edge, bits 0-198 are copied to the
DC/BC/FC data latch and bits 199-215 are copied to the 216-bit DC/BC/FC/UD
shift register. The GSLAT rising edge for a DC/BC/FC/UD data write must be input
more than 7 ms after a data write through the DCSIN pin.
Serial data output of the 288-bit common shift register. LED open detection (LOD),
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LED short detection (LSD), thermal error flag (TEF), and 199-bit data in the
DC/BC/FC data latch can be read via GSSOUT. GSSOUT is connected to the
MSB of the shift register. Data are clocked out at the rising edge of GSSCK.
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Serial data input for the 216-bit DC/BC/FC/UD shift register. DCSIN is connected
to the LSB of the shift register.
Serial data shift clock for the 216-bit DC/BC/FC/UD shift register. Data present on
DCSIN are shifted into the LSB of the shift register with the DCSCK rising edge.
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Data in the shift register are shifted toward the MSB at each DCSCK rising edge.
The MSB data of the register appear on DCSOUT. The 216-bit data in the shift
register are automatically copied to DC/BC/FC/UD data latch 3 ms to 7 ms after
the DCSCK rising edge is not input.
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Serial data output of the 216-bit shift register. DCSOUT is connected to the MSB of
the shift register. Data are clocked out at the rising edge of DCSCK.
Reference clock for the GS pulse width modulation (PWM) control for the RED
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LED output group. When XBLNK is high, each GSCKR rising edge increments the
RED LED GS counter for PWM control.
Reference clock for the GS PWM control for the GREEN LED output group. When
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XBLNK is high, each GSCKR rising edge increments the GREEN LED GS counter
for PWM control.
Reference clock for the GS PWM control for the BLUE LED output group. When
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XBLNK is high, each GSCKR rising edge increments the BLUE LED GS counter
for PWM control.
When XBLNK is low, all constant-current outputs (OUTR0-OUTR7,
OUTG0-OUTG7, OUTB0-OUTB7) are forced off. The grayscale counters for each
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color group are reset to '0', and the grayscale PWM timing controller is initialized.
When XBLNK is high, all constant current outputs are controlled by the grayscale
PWM timing controller for each color LED. This pin is internally pulled to GND with
a 500 kΩ resistor.
I/O
A resistor connected between IREF and GND sets the maximum current for all
constant current outputs.
Constant-current outputs for the RED LED group. These outputs are controlled
with the GSCKR clock signal.
The RED LED group is divided into four subgroups: OUTR0/OUTR4,
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OUTR1/OUTR5, OUTR2/OUTR6, and OUTR3/OUTR7.
Each paired output turns on/off with 24 ns (typ) time delay between other paired
outputs. Multiple outputs can be tied together to increase the constant current
capability. Different voltages can be applied to each output.
Copyright © 2009, Texas Instruments Incorporated
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