TLC5951 Datasheet, PDF (28/46 Pages) Texas Instruments – 24-Channel, 12-Bit PWM LED Driver with 7-Bit Dot Correction and 3-Group, 8-Bit Global Brightness Control

TLC5951
SBVS127B – MARCH 2009 – REVISED DECEMBER 2009
www.ti.com
288-Bit Common Shift Register
The 288-bit common shift register is used to shift data from the GSSIN pin into the TLC5951. The data shifted
into this register are used for grayscale data, global brightness control, and dot correction data. The register LSB
is connected to GSSIN and the MSB is connected to GSSOUT. On each GSSCK rising edge, the data on GSSIN
are shifted into the register LSB and all 288 bits are shifted towards the MSB. The register MSB is always
connected to GSSOUT.
The level of GSLAT at the last GSSCK before the GSLAT rising edge determines which latch the data are
transferred into. When GSLAT is low at the last GSSCK rising edge, all 288 bits are latched into the grayscale
data latch. When GSLAT is high at the last GSSCK rising edge, bits 0-198 are copied to bits 0-198 in the
DC/BC/FC/UD data latch and bits 199-215 are copied to bits 199-215 in the 216-bit DC/BC/FC/UD shift register
at the GSLAT rising edge. To avoid data from being corrupted, the GSLAT rising edge must be input more than
7 ms after the last DCSCK for a DC/BC/FC/UD data write. When the IC powers on, the 288-bit common shift
register contains random data.
Grayscale Data Latch
The grayscale (GS) data latch is 288 bits long. This latch contains the 12-bit PWM grayscale value for each of
the TLC5951 constant-current outputs. The PWM grayscale values in this latch set the PWM on-time for each
constant-current driver. See Table 7 for the on-time duty of each GS data bit. Figure 45 shows the shift register
and latch configuration. Refer to Figure 10 for the timing diagram for writing data into the GS shift register and
latch.
Data are latched from the 288-bit common shift register into the GS data latch at the rising edge of the GSLAT
pin. The conditions for latching data into this register are described in the 288-Bit Common Shift Register section.
When data are latched into the GS data latch, the new data are immediately available on the constant-current
outputs. For this reason, data should only be latched when XBLNK is low. If data are latched with XBLNK high,
the outputs may turn on or off unexpectedly.
MSB
287
276
LSB
47
36
35
24
23
12
11
0
OUTB7
OUTB7
OUTR1
OUTR1 OUTB0
OUTB0 OUTG0
OUTG0 OUTR0
OUTR0
¼
¼
¼
¼
¼
¼
Bit 11
Bit 0
Bit 11
Bit 0 Bit 11
Bit 0 Bit 11
Bit 0 Bit 11
Bit 0
GS Data for OUTB7
GS Data for OUTR1 GS Data for OUTB0 GS Data for OUTG0 GS Data for OUTR0
Figure 45. Grayscale Data Latch Configuration
28
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