TLC5951 Datasheet, PDF (31/46 Pages) Texas Instruments – 24-Channel, 12-Bit PWM LED Driver with 7-Bit Dot Correction and 3-Group, 8-Bit Global Brightness Control

TLC5951
www.ti.com
SBVS127B – MARCH 2009 – REVISED DECEMBER 2009
Function Control Data Latch
The function control (FC) data latch is 7 bits in length and is used to select the dot correction adjustment range,
grayscale counter mode, enabling of the auto display repeat, and display timing reset function. When the IC is
powered on, the data in the FC latch are not set to a specific default value. Therefore, function control data must
be written to the FC data latch before turning on the constant current output.
Table 11. Data Bit Assignment
BIT
192
193
194
195
196
198, 197
DESCRIPTION
Dot correction adjustment range for the RED color output (0 = lower range, 1 = higher range).
When this bit is '0', dot correction can control the range of constant current by 0% to 66.7% (typ) of the maximum current set
by an external resistor. This mode only operates the output for the red LED driver group.
When this bit is '1', dot correction can control the range of constant current by 33.3% (typ) to 100% of the maximum current set
by an external resistor.
Dot correction adjustment range for the GREEN color output (0 = lower range, 1 = higher range).
When this bit is '0', dot correction can control the range of constant current by 0% to 66.7% (typ) of the maximum current set
by an external resistor. This mode only operates the output for the green LED driver group.
When this bit is '1', dot correction can control the range of constant current by 33.3% (typ) to 100% of the maximum current set
by an external resistor.
Dot correction adjustment range for the BLUE color output (0 = lower range, 1 = higher range).
When this bit is '0', dot correction can control the range of constant current by 0% to 66.7% (typ) of the maximum current set
by an external resistor. This mode only operates the output for the blue LED driver group.
When this bit is '1', dot correction can control the range of constant current by 33.3% (typ) to 100% of the maximum current set
by an external resistor.
Auto display repeat mode (0 = disabled, 1 = enabled).
When this bit is '0', the auto repeat function is disabled. Each output driver is turned on and off once after XBLNK goes high.
When this bit is '1', each output driver is repeatedly toggled on/off every 4096th grayscale clock without the XBLNK level
changing when the GS counter is configured as a 12-bit mode. If the GS counter is configured as a 10-bit mode, the outputs
continue to cycle on/off every 1024th grayscale clock. If the GS counter is set to the 8-bit mode, the output on/off repetition
cycles every 256th grayscale clock.
Display timing reset mode (0 = disabled, 1 = enabled).
When this bit is '1', the GS counter is reset to '0' and all outputs are forced off at the GSLAT rising edge for a GS data write.
This function is identical to the low pulse of the XBLNK signal when input. Therefore, the XBLNK signal is not needed to
control from a display controller. PWM control starts again from the next input GSCKR/G/B rising edge.
When this bit is '0', the GS counter is not reset and no outputs are forced off even if a GSLAT rising edge is input. In this
mode, the XBLNK signal should be input after the PWM control of all LED are finished. Otherwise, the PWM control might be
not exact.
Grayscale counter mode select, bits 1-0.
The grayscale counter mode is selected by the setting of bits 1 and 0. Table 12 shows the GS counter mode.
Table 12. GS Counter Mode Truth Table
GRAYSCALE COUNTER MODE
BIT 1
BIT 0
0
X (don't care)
1
0
1
1
FUNCTION MODE
12-bit counter mode (maximum output on-time = 4095 × GS clock)
10-bit counter mode (maximum output on-time = 1023 × GS clock)
8-bit counter mode (maximum output on-time = 255 × GS clock)
The grayscale data latch bit length is always 288 bits in any grayscale counter mode. All constant-current outputs
are forced off at the 256th grayscale clock in the 8-bit mode even if all grayscale data are FFFh. In 10-bit mode,
all outputs are forced off at 1024th grayscale clock even if all grayscale data are FFFh.
Copyright © 2009, Texas Instruments Incorporated
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