TLC5951 Datasheet, PDF (27/46 Pages) Texas Instruments – 24-Channel, 12-Bit PWM LED Driver with 7-Bit Dot Correction and 3-Group, 8-Bit Global Brightness Control

TLC5951
www.ti.com
SBVS127B – MARCH 2009 – REVISED DECEMBER 2009
REGISTER AND DATA LATCH CONFIGURATION
The TLC5951 has two data latches to store information: the grayscale (GS) data latch and the DC/BC/FC/UD
data latch. The GS data latch can be written as 288-bit data through GSSIN with GSSCK. The DC/BC/FC/UD
data latch can be written as data through DCSIN with DCSCK. Also, DC/BC/FC data can be written to the
DC/BC/FC/UD data latch through GSSIN with GSSCK. UD data are written to the upper 17 bits of the 216-bit
DC/BC/FC/UD shift register at the same time. The data in the DC/BC/FC/UC data latch can be read via
GSSOUT with GSSCK. Figure 44 shows the grayscale shift register and data latch configuration.
From LSD/LOD/TEF Data Holder
From 216-Bit DC/BC/FC/UD Data Latch
49
288-Bit Common Shift Register
These 49 bits of data are loaded into the
upper 49 bits of the 288-bit shift register
when GSLAT is low at the last GSSCK
rising edge before the rising edge of GSLAT.
These 216 bits of data are loaded into the
216 ^{lower 216 bits of the 288-bit shift register when}
GSLAT is low at the last GSSCK rising edge
before the rising edge of GSLAT.
GSSOUT
MSB
LSB
Common Common Common Common Common Common
Common Common Common Common Common Common
Data Bit Data Bit Data Bit Data Bit Data Bit Data Bit
¼
Data Bit Data Bit Data Bit Data Bit Data Bit Data Bit
287
286
285
284
283
282
5
4
3
2
1
0
GSSIN
GSSCK
DCSOUT
288
Lower 216 Bits of 288 Bits
288
Grayscale Data Latch (12 Bits ´ 24 Channels)
MSB
287
276
LSB
47
36
35
24
23
12
11
0
OUTB7 _¼ OUTB7 _¼ OUTR1 _¼ OUTR1 OUTB0 _¼ OUTB0 OUTG0 _¼ OUTG0 OUTR0 _¼ OUTR0
Bit 11
Bit 0
Bit 11
Bit 0 Bit 11
Bit 0 Bit 11
Bit 0 Bit 11
Bit 0
GS Data for OUTB7
GS Data for OUTR1 GS Data for OUTB0 GS Data for OUTG0 GS Data for OUTR0
288
This latch
pulse is
generated
when GSLAT
is low at the
last GSSCK
rising edge
before the
GSLAT
rising edge.
Upper 17 Bits of 216 Bits
To PWM Timing Control Block for Each Color
These 17 bits of data are loaded into the upper 17 bits of the 216-bit shift register when GSLAT
is high at the last GSSCK rising edge before the GSLAT rising edge. The other bits remain unchanged.
MSB
215
214
Data Data
Bit 215 Bit 214
¼ ₁₉₇
196
195
5
¼ ^{Data Data Data} ¼ ^Data
Bit 197 Bit 196 Bit 195
Bit 5
4
Data
Bit 4
216-Bit DC/BC/FC/UD Shift Register
3
Data
Bit 3
2
Data
Bit 2
1
Data
Bit 1
0
Data
Bit 0
DCSIN
DCSCK
Lower 199 Bits of 216 Bits
These 199 bits of data are loaded into the lower 199 bits of the
216-bit shift register when GSLAT is high at the last GSSCK
rising edge before the GSLAT rising edge. The User Defined
bit data in the 216-bit data latch remain unchanged.
These 216 bits of data are automatically loaded into the
216 _{216-bit data latch by the latch pulse generated 3ms-7ms}
after the DCSCK rising edge is not input.
Dot Correction (7 Bits ´ 24 Channels)/
Global Brightness Control (8 Bits ´ 3 Group)/
Function Control (7 Bits)
User Defined (17 Bits)
216-Bit DC/BC/FC/UD Data Latch
MSB
LSB
215-199 198-192 191-184 183-176 175-168 167-161 160-154 153-147
27-21 20-14 13-7 6-0
¼ ^User
Defined
Bits 16-0
FUNC
Bits 6-0
BRIGHT BRIGHT BRIGHT DOTCOR DOTCOR DOTCOR
Bits 7-0 Bits 7-0 Bits 7-0 Bits 6-0 Bits 6-0 Bits 6-0
OUTB0-7 OUTG0-7 OUTR0-7 OUTB7 OUTG7 OUTR7
DOTCOR DOTCOR DOTCOR DOTCOR
Bits 6-0 Bits 6-0 Bits 6-0 Bits 6-0
OUTR1 OUTB0 OUTG0 OUTR0
Function Global Brightness Control
Control
Dot Correction
216
This latch pulse is generated when
GSLAT is high at the last GSSCK
rising edge before the GSLAT
rising edge. Otherwise, the latch
pulse is generated 3 ms to 7 ms
after the DCSCK rising edge.
7
24
216
171
To GS Counter/PWM Timing To Global Brightness To 288-Bit Common
Control Block
Control Block
Shift Register
To Dot Correction
Control Block
Figure 44. Grayscale Shift Register and Data Latch Configuration
Copyright © 2009, Texas Instruments Incorporated
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