TLC5951 Datasheet, PDF (24/46 Pages) Texas Instruments – 24-Channel, 12-Bit PWM LED Driver with 7-Bit Dot Correction and 3-Group, 8-Bit Global Brightness Control

TLC5951
SBVS127B – MARCH 2009 – REVISED DECEMBER 2009
www.ti.com
GRAYSCALE (GS) FUNCTION (PWM CONTROL)
The TLC5951 can adjust the brightness of each output channel using a pulse width modulation (PWM) control
scheme. The use of 12 bits per channel results in 4096 brightness steps, from 0% up to 100% brightness. The
grayscale circuitry is duplicated for each of the three color groups.
The PWM operation for each color group is controlled by a 12-bit GS counter. Three GS counters are
implemented to control each of the three color outputs, OUTR0-OUTR7, OUTG0-OUTG7, and OUTB0-OUTB7.
Each counter increments on each rising edge of the grayscale reference clock (GSCKR, GSCKG, or GSCKB).
The falling edge of XBLNK resets the three counter values to '0'. The grayscale counter values are held at '0'
while XBLNK is low, even if the GS clock input is toggled high and low. Pulling XBLNK high enables the GS
clock. The first rising edge of a GS clock after XBLNK goes high increments the corresponding grayscale counter
by one and switches on all outputs with a non-zero GS value programmed into the GS latch. Each additional
rising edge on a GS clock increases the corresponding GS counter by one.
The GS counters keep track of the number of clock pulses from the respective GS clock inputs (GSCKR,
GSCKG, and GSCKB). Each output stays on while the counter is less than or equal to the programmed
grayscale value. Each output turns off at the rising edge of the GS counter value when the counter is larger than
the output grayscale latch value.
Equation 4 calculates each output (OUTRn/Gn/Bn) on-time (t_{OUT_ON}):
t_OUTON (ns) = T_GSCLKR/G/B (ns) ´ GSn
(4)
Where:
T_GSCKR/G/B = one period of GS clock for the color
GSn = the programmed grayscale value for OUTRn/Gn/Bn (GSn = 0d to 4095d)
When new GS data are latched into the GS data latch with the rising edge on GSLAT during a PWM cycle, the
GS data latch registers are immediately updated. This latching can cause the outputs to turn on or off
unexpectedly. For proper operation, GS data should only be latched into the IC at the end of a display period
when XBLNK is low. Table 7 summarizes the GS data value versus the output on-time duty cycle.
When the IC is powered up, the 288-bit common shift register and GS data latch contain random data.
Therefore, GS data must be written to the GS latch before turning the constant-current output on. Additionally,
XBLNK should be low when the device is powered up to prevent the outputs from turning on before the proper
GS values are programmed into the registers. All constant-current outputs are off when XBLNK is low.
If there are any unconnected outputs (OUTRn, OUTGn, and OUTBn), including LEDs in a failed short or failed
open condition, the GS data corresponding to the unconnected output should be set to '0' before turning on the
LEDs. Otherwise, the VCC supply current (I_VCC) increases while that constant-current output is programmed to
be on.
GS DATA
(Binary)
0000 0000 0000
0000 0000 0001
0000 0000 0010
—
0111 1111 1111
1000 0000 0000
1000 0000 0001
—
1111 1111 1101
1111 1111 1110
1111 1111 1111
Table 7. Output Duty Cycle and On-Time versus GS Data
GS DATA
(Decimal)
0
1
2
—
2047
2048
2049
—
4093
4094
4095
GS DATA
(Hex)
000
001
002
—
7FF
800
801
—
FFD
FFE
FFF
OUTPUT ON-TIME DUTY
CYCLE (%)
0
0.02
0.05
—
49.99
50.01
50.04
—
99.95
99.98
100
OUTPUT ON-TIME
(33-MHz GS Clock) (ns)
0
30
61
—
62030
62061
62091
—
124030
124061
124091
24
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