DS90C187_14 Datasheet, PDF (9/28 Pages) Texas Instruments – Low Power 1.8V Dual Pixel FPD-Link (LVDS) Serializer

DS90C187
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AC Timing Diagrams
SNLS401B – FEBRUARY 2012 – REVISED APRIL 2013
T
IN_CLK
INn_x,
n = A or B,
x = ODD
INn_x,
n = A or B,
x = EVEN
Falling Edge CLK (RFB = GND) shown
A. The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/ I/O.
B. Figure 2 and Figure 3 show a falling edge data strobe (IN_CLK).
Figure 2. Checker Board Test Pattern
Signal
Signal Pattern
Signal Frequency
PCLK
f
R0
f / 16
R1
f/8
R2
f/4
R3
f/2
R4
Steady State, Low
R5
Steady State, Low
G0
f / 16
G1
f/8
G2
f/4
G3
f/2
G4
Steady State, Low
G5
Steady State, Low
B0
f / 16
B1
f/8
B2
f/4
B3
f/2
B4
Steady State, Low
B5
Steady State, Low
HS
Steady State, High
VS
Steady State, High
DE
Steady State, High
A. The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/ I/O.
B. Recommended pin to signal mapping for 18 bits per pixel, customer may choose to define differently. The 16
grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
C. Figure 2 and Figure 3 show a falling edge data strobe (IN_CLK).
Figure 3. “16 Gray Scale” Test Pattern (Falling Edge Clock shown)
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