DS90C187_14 Datasheet, PDF (8/28 Pages) Texas Instruments – Low Power 1.8V Dual Pixel FPD-Link (LVDS) Serializer

DS90C187
SNLS401B – FEBRUARY 2012 – REVISED APRIL 2013
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Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Unit
TSTC
INn_x Setup to IN_CLK
Figure 7
0
ns
THTC
INn_x Hold from IN_CLK
2.5
ns
LLHT
LVDS Low-to-High Transition Time
Figure 5 ⁽¹⁾
0.18
0.5
ns
LHLT
LVDS High-to-Low Transition Time
Figure 5 ⁽¹⁾
0.18
0.5
ns
TBIT
LVDS Output Bit Width
MODE[1:0] = 00, or 10
1/7 TCIP
ns
MODE[1:0] = 01
2/7 TCIP
ns
TPPOS0 Transmitter Output Pulse Positions Normalized
for Bit 0
Figure 10
1
UI
TPPOS1 Transmitter Output Pulse Positions Normalized
for Bit 1
2
UI
TPPOS2 Transmitter Output Pulse Positions Normalized
for Bit 2
3
UI
TPPOS3 Transmitter Output Pulse Positions Normalized
for Bit 3
4
UI
TPPOS4 Transmitter Output Pulse Positions Normalized
for Bit 4
5
UI
TPPOS5 Transmitter Output Pulse Positions Normalized
for Bit 5
6
UI
TPPOS6 Transmitter Output Pulse Positions Normalized
for Bit 6
7
UI
ΔTPPOS Variation in Transmitter Pulse Position (Bit 6 —
Bit 0)
±0.06
UI
TCCS
LVDS Channel to Channel Skew
110
ps
TJCC
Jitter Cycle-to-Cycle
MODE0, MODE1 = 0,
f = 105 MHz,
(1)
0.028
0.035
UI
TPLLS
TPDD
Phase Lock Loop Set (Enable Time)
Powerdown Delay
Figure 8
Figure 9
(2)
1
ms
100
ns
TSD
Latency Delay
MODE0 = 0,
MODE1 = 1 or 0
Figure 11
(1)
2*TCIP + 2*TCIP +
ns
10.54
13.96
TLAT
Latency Delay for Single Pixel In / Dual Pixel Out MODE0 = 1,
Mode
MODE1 = 0
Figure 11
(1)
9*TCIP + 9*TCIP +
ns
4.19
6.36
(1) Parameter is guaranteed by characterization and is not tested at final test.
(2) Parameter is guaranteed by design and is not tested at final test.
8
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