DS90C187_14 Datasheet, PDF (10/28 Pages) Texas Instruments – Low Power 1.8V Dual Pixel FPD-Link (LVDS) Serializer

DS90C187
SNLS401B – FEBRUARY 2012 – REVISED APRIL 2013
AC Timing Diagrams (continued)
OA/B_C+, OA/B_[3:0]+
100:
OA/B_C-, OA/B_[3:0]-
Figure 4. DS90C187 (Transmitter) LVDS Output Load
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80%
VSS = 2|VOD|
80%
20%
20%
LLHT
LHLT
Figure 5. LVDS Output Transition Times
+VOD
0V
-VOD
80%
80%
VDD
50%
20%
TCIT, or
TXIT
20%
TCIT, or
TXIT
GND
Figure 6. LVCMOS Input Transition Times
TCIP
VIHmin
TSTC
VILmax
THTC
TCIH
TCIL
VDD
50%
GND
VDD
50%
GND
Falling Edge CLK shown (RFB = GND)
Figure 7. LVCMOS Input Setup/Hold and Clock High/Low Times (Falling Edge Strobe)
VDD
IN_CLK
PDB
OCA/B
(Diff.)
TPLLS
1.8V
GND
VDD
GND
VDD
GND
(LVDS)
Figure 8. Start Up / Phase Lock Loop Set Time
10
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