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| DS90C187_14 Datasheet, PDF (17/28 Pages) Texas Instruments – Low Power 1.8V Dual Pixel FPD-Link (LVDS) Serializer | |||
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DS90C187
www.ti.com
SNLS401B â FEBRUARY 2012 â REVISED APRIL 2013
Table 4. Dual Pixel Input / 24bpp (continued)
DS90C187 Input
INA_12
INB_22
INB_21
INB_5
INB_4
INB_3
INB_2
INB_1
INB_0
INB_24
INB_23
INB_11
INB_10
INB_9
INB_8
INB_7
INB_6
INB_26
INB_25
INB_17
INB_16
INB_15
INB_14
INB_13
INB_12
DE
VS
HS
INA_27
INB_27
Color Mapping
O_B0
E_R7
E_R6
E_R5
E_R4
E_R3
E_R2
E_R1
E_R0
E_G7
E_G6
E_G5
E_G4
E_G3
E_G2
E_G1
E_G0
E_B7
E_B6
E_B5
E_B4
E_B3
E_B2
E_B1
E_B0
DE
VS
HS
GP
GP
Note
Data Enable*
Vertical Sync
Horizontal Sync
General Purpose
General Purpose
FUNCTIONAL DESCRIPTION
DS90C187 converts a wide parallel LVCMOS input bus into banks of FPD-Link LVDS data. The device can be
configured to support RGB-888 (24 bit color) or RGB-666 (18 bit color) in three main configurations: single pixel
in / single pixel out; single pixel in / dual pixel out; dual pixel in / dual pixel out. The DS90C187 has several
power saving features including: selectable VOD, 18 bit / 24 bit mode select, and a power down pin control.
Device Configuration
The MODE0 and MODE1 pins are used to configure the DS90C187 into the three main operation modes as
shown in the table below.
MODE1
0
0
1
1
Table 5. Mode Configurations
MODE0
0
1
0
1
CONFIGURATION
Single Pixel Input, Single Pixel Output (SISO)
Single Pixel Input, Dual Pixel Output (SIDO)
Dual Pixel Input, Dual Pixel Output (DIDO)
RESERVED
Copyright © 2012â2013, Texas Instruments Incorporated
Product Folder Links: DS90C187
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