DS90C187_14 Datasheet, PDF (11/28 Pages) Texas Instruments – Low Power 1.8V Dual Pixel FPD-Link (LVDS) Serializer

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DS90C187
SNLS401B – FEBRUARY 2012 – REVISED APRIL 2013
AC Timing Diagrams (continued)
IN_CLK
PDB
OCA/B
(Diff.)
50%
TPDD
GND
VDD
GND
VDD
GND
(LVDS)
Figure 9. Sleep Mode / Power Down Delay
OA_C+/-,
or OB_C+/-
Cycle N
OA[3:0]+/-, or
OB[3:0]+/-
bit 1
bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
n-1
n-1
n
n
n
n
n
n
n
1UI
2UI
3UI
4UI
5UI
6UI
7UI
Figure 10. LVDS Serial Bit Positions
IN_CLK
INA/Bn
DE
OA/B_C+/-
OA_n+/-
OB_n+/-
Pixel 1
Pixel 2
Pixel 3
Pixel 4
TLAT
Pixel 1
Pixel 2
Pixel 3
Pixel 4
Figure 11. Single In Dual Out Mode Timing and Latency
IN_CLK
INA/B
Pixel n-1
Pixel n
Pixel n+1
Pixel n+2
Pixel n+3
OA/B_C+/-
OA/B_n+/-
TSD
Pixel n
Pixel n+1
Figure 12. Single In Single Out / Dual In Dual Out Latency
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