DS90C187_14 Datasheet, PDF (12/28 Pages) Texas Instruments – Low Power 1.8V Dual Pixel FPD-Link (LVDS) Serializer

DS90C187
SNLS401B – FEBRUARY 2012 – REVISED APRIL 2013
AC Timing Diagrams (continued)
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110
VODSEL = L, 18B = L
100
VODSEL = H, 18B = L
VODSEL = L, 18B = H
VODSEL = H, 18B = H
90
80
70
60
50
40
30
40 60 80 100 120 140 160 180 200
FREQUENCY (MHz)
Figure 13. Typ Current Draw — Single In/Dual Out Mode — PRBS-7 Data Pattern
60
55
50
45
40
35
30
25
20
20
VODSEL = L, 18B = L
VODSEL = H, 18B = L
VODSEL = L, 18B = H
VODSEL = H, 18B = H
40 60 80 100 120
FREQUENCY (MHz)
Figure 14. Typ Current Draw — Single In/Single Out Mode — PRBS-7 Data Pattern
LVDS INTERFACE / TFT COLOR DATA RECOMMENDED MAPPING
Different color mapping options exist. Check with the color mapping of the Deserializer / TCON device that is
used to ensure compatible mapping for the application. The DS90C187 supports three modes of operation for
single and dual pixel applications supporting either 24bpp or 18bpp color depths.
In the Dual Pixel / 24bpp mode, eight LVDS data lines are provided along with two LVDS clock lines (8D+2C).
The Deserializer may utilize one or two clock lines. The 53 bit interface typically assigns 24 bits to RGB for the
odd pixel, 24 bits to RGB for the even pixel, 3 bits for the video control signals (HS, VS and DE), 1 bit for odd
pixel and 1 bit for even pixel which can be ignored or used for general purpose data, control or L/R signaling.
A reduced width input interface is also supported with a Single-to-Dual Pixel conversion where the data is
presented at double rate (same clock edge, 2X speed, see Figure 11) and the DE transition is used is flag the
first pixel. Also note in both 8D+2C configurations, the three video control signals are sent over both the A and B
outputs. The DES / TCON may recover one set, or both depending upon its implementation. The Dual Pixel /
24bpp 8D+2C LVDS Interface Mapping is shown in Figure 15.
A Dual Pixel / 18bpp mode is also supported. In this configuration OA3 and OB3 LVDS output channels are
placed in TRI-STATE® to save power. Their respective inputs are ignored. (Figure 16)
In the Single Pixel / 24bpp mode, four LVDS data lines are provided along with a LVDS clock line (4D+C). The
28 bit interface typically assigns 24 bits to RGB color data, 3 bits to video control (HS, VS and DE) and one
spare bit can be ignored, used for L/R signaling or function as a general purpose bit. The Single Pixel / 24bpp
4D+C LVDS Interface Mapping is shown in Figure 17.
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