DS50PCI402_14 Datasheet, PDF (9/35 Pages) Texas Instruments – 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis

DS50PCI402
www.ti.com
SNLS320G – APRIL 2010 – REVISED MAY 2011
Manual Control Of RXDETA/B In A PCIe Environment
In some cases manual control of RXDETA/B may be desirable. In order for upstream and downstream PCIe
subsystems to communicate in a cabling environment, the PCIe specification includes several auxiliary or
sideband signals to manage system-level functionality or implementation. Similar methods are used in backplane
applications, but the exact implementation falls outside the PCIe standard. Initial communication from the
downstream subsystem to the upstream subsystem is done with the CPRSNT# auxiliary signal. The CPRSNT#
signal is asserted Low by the downstream componentry after the "Power Good" condition has been established.
This mechanism allows for the upstream subsystem to determine whether the power is good within the
downstream subsystem, enable the reference clock, and initiate the Link Training Sequence.
CPWRON
CPERST#
CPRSNT# to RESET Removal
DS50PCI402 PRSNT#
Min pulse width HIGH
5 Ps (min)
CPRSNT#
5 ms (min)
0V
0V
RESET Removed and
REFCLK Stable
0V
CREFCLK
Figure 3. Typical PCIe System Timing
The signals shown in the graphic could be easily replicated within the downstream subsystem and used to
externally control the common mode input termination impedance on the DS50PCI402. Often an onboard
microcontroller will be used to handle events like power-up, power-down, power saving modes, and hot insertion.
The microcontroller would use the same information to determine when to enable and disable the DS50PCI402
input termination. In applications that require SMBus control, the microcontroller could also delay any response
to the upstream subsystem to allow sufficient time to correctly program the DS50PCI402 and other devices on
the board.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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