DS50PCI402_14 Datasheet, PDF (19/35 Pages) Texas Instruments – 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis

DS50PCI402
www.ti.com
0x01
PWDN Channels
0x02
PWDN Control
0x08
Pin Control Override
0x0E
CH0 - CHB0
IDLE RATE Select
0x0F
CH0 - CHB0
EQ Control
0x10
CH0 - CHB0
VOD Control
SNLS320G – APRIL 2010 – REVISED MAY 2011
Table 9. SMBus Register Map (continued)
7:0 PWDN CHx
7:1 Reserved
0
Override PWDN
7:5 Reserved
4
Override IDLE
3
Reserved
2
Override RATE
1:0 Reserved
7:6 Reserved
5
IDLE auto
4
IDLE select
3:2 Reserved
1
RATE auto
0
RATE select
7:6 Reserved
5:0 CH0 IB0 EQ
7
Reserved
5:0 CH0 OB0 VOD
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x20
R/W 0x03
Power Down per Channel
[7]: CHA_3
[6]: CHA_2
[5]: CHA_1
[4]: CHA_0
[3]: CHB_3
[2]: CHB_2
[1]: CHB_1
[0]: CHB_0
00'h = all channels enabled
FF'h = all channels disabled
Set bits to 0.
0: Allow PWDN pin control
1: Block PWDN pin control
Set bits to 0.
0: Allow IDLE pin control
1: Block IDLE pin control
Set bit to 0.
0: Allow RATE pin control
1: Block RATE pin control
Set bits to 0.
Set bits to 0.
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
Set bits to 0.
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0: 2.5 Gbps
1: 5.0 Gbps
Set bits to 0.
IB0 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Pin [EQ1 EQ0] = Register [EN] [GST] [BST] = Hex
Value
FF = 100000 = 20'h = Bypass (Default)
11 = 101010 = 2A'h
00 = 110000 = 30'h
F0 = 110010 = 32'h
10 = 111001 = 39'h
F1 = 110101 = 35'h
01 = 110111 = 37'h
0F = 111011 = 3B'h
1F = 111101 = 3D'h
Set bit to 0.
OB0 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
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