DS50PCI402_14 Datasheet, PDF (3/35 Pages) Texas Instruments – 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis

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Pin Diagram
DS50PCI402
SNLS320G – APRIL 2010 – REVISED MAY 2011
OB_0+ 1
OB_0- 2
OB_1+ 3
OB_1- 4
OB_2+ 5
OB_2- 6
OB_3+ 7
OB_3- 8
VDD 9
IA_0+ ¹⁰
IA_0- ¹¹
IA_1+ 12
IA_1- 13
VDD 14
IA_2+ 15
IA_2- 16
IA_3+ ¹⁷
IA_3- 18
SMBUS AND CONTROL
DAP = GND
45 IB_0+
44 IB_0-
43 IB_1+
42 IB_1-
41 VDD
40 IB_2+
39 IB_2-
38 IB_3+
37 IB_3-
36 VDD
35 OA_0+
34 OA_0-
33 OA_1+
32 OA_1-
31 OA_2+
30 OA_2-
29 OA_3+
28 OA_3-
The center DAP on the package bottom is the device GND connection. This pad must be connected to GND through
multiple (minimum of 8) vias to ensure optimal electrical and thermal performance.
Figure 1. DS50PCI402 Pin Diagram 54 lead
Pin Functions
Pin Name
Pin Number
Differential High Speed I/O's
IA_0+, IA_0- ,
IA_1+, IA_1-,
IA_2+, IA_2-,
IA_3+, IA_3-
10, 11
12, 13
15, 16
17, 18
Pin Descriptions
I/O,
Type ^{(1) (2) (3) (4)}
Pin Description
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. A
gated on-chip 50Ω termination resistor connects INA_0+ to VDD and
INA_0- to VDD when enabled.
(1) FLOAT = 3rd input state, don't drive pin. Pin is internally biased to mid level with 50 kΩ pull-up/pull-down. If high Z output not available,
drive input to VDD/2 to assert mid level state.
(2) Internal pulldown = Internal 30 kΩ pull-down resistor to GND is present on the input.
(3) LVCMOS inputs without the “Float” conditions must be driven to a logic Low or High at all times or operation is not guaranteed.
(4) Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
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