DS50PCI402_14 Datasheet, PDF (5/35 Pages) Texas Instruments – 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis

DS50PCI402
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Pin Name
ENRXDET
TXIDLEA,TXIDLEB
Analog
SD_TH
Power
VDD
GND
Pin Number
26
24,25
SNLS320G – APRIL 2010 – REVISED MAY 2011
Pin Descriptions (continued)
I/O,
Type ^{(1) (2) (3) (4)}
I, LVCMOS
w/internal
pulldown
I, FLOAT,
LVCMOS
Pin Description
Enables pin control of receiver detect function. The default is automatic
RXDET using the internal pulldown. Pin must be pulled high for manual
RXDETA/B operation. Controls individual A and B sides. Refer to
Table 6.
Controls the electrical idle function on corresponding outputs when
enabled. H= electrical Idle, Float=autodetect (Idle on input passed to
output), L=Idle squelch disabled as shown in Table 5.
27
I, ANALOG
Threshold select pin for electrical idle detect threshold. Float pin for
default 130mV DIFF p-p, otherwise connect resistor from SD_TH to GND
to set threshold voltage as shown in Table 6.
9, 14,36, 41, 51
DAP
Power
Power
Power supply pins CML/analog.
Ground pad (DAP - die attach pad).
Functional Description
The DS50PCI402 is a low power media compensation 4 lane repeater optimized for PCI Express Gen 1 and Gen
2 media including lossy FR-4 printed circuit board backplanes and balanced cables. The DS50PCI402 operates
in two modes: Pin Control Mode (ENSMB = 0) and SMBus Mode (ENSMB = 1).
Pin Control Mode:
When in pin mode (ENSMB = 0) , the repeater is configurable with external pins. Equalization and de-emphasis
can be selected via pin for each side independently. When de-emphasis is asserted VOD is automatically
increased per the De-Emphasis table below for improved performance over lossy media. The receiver detect
pins RXDETA/B provide manual control for input termination (50Ω or >50KΩ). Rate optimization is also pin
controllable, with pin selections for 2.5Gbps, 5Gbps, and auto detect. The receiver electrical idle detect threshold
is also programmable via an optional external resistor on the SD_TH pin.
SMBUS Mode:
When in SMBus mode the equalization, de-emphasis, and termination disable features are all programmable on
a individual lane basis, instead of grouped by sides as in the pin mode case. Upon assertion of ENSMB the
RATE, EQx and DEMx functions revert to register control immediately. The EQx and DEMx pins are converted to
AD0-AD3 SMBus address inputs. The other external control pins remain active unless their respective registers
are written to and the appropriate override bit is set, in which case they are ignored until ENSMB is driven low.
On powerup and when ENSMB is driven low all registers are reset to their default state. If PRSNT is asserted
while ENSMB is high, the registers retain their current state.
Equalization settings accessible via the pin controls were chosen to meet the needs of most PCIe applications. If
additional fine tuning or adjustment is needed, additional equalization settings can be accessed via the SMBus
registers. Each input has a total of 24 possible equalization settings. The tables show a typical gain for each gain
stage (GST[1:0]) and boost level (BST[2:0]) combination. When using SMBus mode, the Equalization and De-
Emphasis levels are set using registers.
Table 1. Equalization Settings with GST=1 for Pins or SMBus Registers
EQ1
F
1
EQ0
F
1
EQ Setting
GST[1 BST[2:
:0]
0]
00
000
01
000
01
001
01
010
01
011
01
100
EQ Gain (dB)
1.25 GHz
2.5 GHz
0
0
1.6
3.2
2.1
4.2
2.6
5.0
3.2
5.9
4.0
7.3
Suggested Use
Bypass - Default Setting
8" FR4 (6-mil trace) or < 1m (28 AWG) PCIe cable
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