DS50PCI402_14 Datasheet, PDF (27/35 Pages) Texas Instruments – 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis

DS50PCI402
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0x43
CH7 - CHA3
DE Control
0x44
CH7 - CHA3
IDLE Threshold
0x47
Global VOD Adjust
SNLS320G – APRIL 2010 – REVISED MAY 2011
Table 9. SMBus Register Map (continued)
7:0 CH7 OA3 DEM
7:4 Reserved
3:0 IDLE threshold
7:2 Reserved
1:0 VOD Adjust
R/W 0x03
R/W 0x00
R/W 0x02
OA3 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced = 1)
[6:0]: DEM Level Control
Pin [DEM1 DEM0] = Register [TYPE] [Level Control]
= Hex Value
00 = 00000001 = 01'h = 0.0 dB
01 = 11101000 = E8'h = −3.5 dB
11 = 10001000 = 88'h = −6.0 dB
0F = 10010000 = 90'h = −9.0 dB
1F = 10100000 = A0'h = −12.0 dB
F0 = 10010000 = 90'h = −9.0 dB
F1 = 10100000 = A0'h = −12.0 dB
FF = 11000000 = C0'h = Reserved
Set bits to 0.
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
Set bits to 0.
00 = -25.0%
01 = -12.5%
10 = +0.0% (Default)
11 = +12.5%
Applications Information
GENERAL RECOMMENDATIONS
The DS50PCI402 is a high performance circuit capable of delivering excellent performance. Careful attention
must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer
to the information below and the latest version of the LVDS Owner's Manual for more detailed information on
high speed design tips to address signal integrity design issues.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS
The CML inputs and LPDS outputs have been optimized to work with interconnects using a controlled differential
impedance of 85 - 100Ω. It is preferable to route differential lines exclusively on one layer of the board,
particularly for the input traces. The use of vias should be avoided if possible. If vias must be used, they should
be used sparingly and must be placed symmetrically for each side of a given differential pair. Whenever
differential vias are used the layout must also provide for a low inductance path for the return currents as well.
Route the differential signals away from other signals and noise sources on the printed circuit board. See AN-
1187 for additional information on LLP packages.
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