DS50PCI402_14 Datasheet, PDF (16/35 Pages) Texas Instruments – 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis

DS50PCI402
SNLS320G – APRIL 2010 – REVISED MAY 2011
www.ti.com
t_LOW
t_R
t_BUF
t_HD:STA
t_HD:DAT
t_HIGH
t_F
t_SU:DAT
t_SU:STA
t_SU:STO
SP
ST
ST
SP
Figure 8. SMBus Timing Parameters
SCL
SDA
System Management Bus (SMBus) and Configuration Registers
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. ENSMB must be
pulled high to enable SMBus mode and allow access to the configuration registers.
The DS50PCI402 has the AD[3:0] inputs in SMBus mode. These pins are the user set SMBus slave address
inputs. The AD[3:0] pins have internal pull-down. When left floating or pulled low the AD[3:0] = 0000'b, the device
default address byte is A0'h. Based on the SMBus 2.0 specification, the DS50PCI402 has a 7-bit slave address
of 1010000'b. The LSB is set to 0'b (for a WRITE), thus the 8-bit value is 1010 0000'b or A0'h. The device
address byte can be set with the use of the AD[3:0] inputs. Below are some examples.
AD[3:0] = 0001'b, the device address byte is A2'h
AD[3:0] = 0010'b, the device address byte is A4'h
AD[3:0] = 0100'b, the device address byte is A8'h
AD[3:0] = 1000'b, the device address byte is B0'h
The SDA, SCL pins are 3.3V tolerant, but are not 5V tolerant. External pull-up resistor is required on the SDA.
The resistor value can be from 1 kΩ to 5 kΩ depending on the voltage, loading and speed. The SCL may also
require an external pull-up resistor and it depends on the Host that drives the bus.
TRANSFER OF DATA VIA THE SMBus
During normal operation the data on SDA must be stable during the time when SCL is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SCL is High indicates a message START condition.
STOP: A Low-to-High transition on SDA while SCL is High indicates a message STOP condition.
IDLE: If SCL and SDA are both High for a time exceeding t_BUF from the last detected STOP condition or if they
are High for a total exceeding the maximum specification for t_HIGH then the bus will transfer to the IDLE state.
SMBus TRANSACTIONS
The device supports WRITE and READ transactions. See Register Description table for register address, type
(Read/Write, Read Only), default value and function information.
When SMBus is enabled, the DS50PCI402 must use one of the following De-emphasis settings (Table 8).
The driver de-emphasis value is set on a per channel basis using 8 different registers. Each register (0x11, 0x18,
0x1F, 0x26, 0x2E, 0x35, 0x3C, 0x43) requires one of the following De-emphasis settings when in SMBus mode.
See Table 4 for suggested DE settings at 2.5 and 5.0 Gbps operation.
Table 8. De-Emphasis Register Settings (must write one of the following when in SMBus mode)
De-Emphasis Value
0.0 dB
-3.5 dB
-6 dB
-9 dB
Register Setting
0x01
0xE8
0x88
0x90
16
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