DS50PCI402_14 Datasheet, PDF (14/35 Pages) Texas Instruments – 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis

DS50PCI402
SNLS320G – APRIL 2010 – REVISED MAY 2011
Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
SERIAL BUS INTERFACE DC SPECIFICATIONS
V_IL
Data, Clock Input Low Voltage
V_IH
Data, Clock Input High Voltage
2.1
I_PULLUP
Current Through Pull-Up Resistor High Power Specification
or Current Source
4
V_DD
I_LEAK-Bus
I_LEAK-Pin
C_I
R_TERM
Nominal Bus Voltage
Input Leakage Per Bus Segment
Input Leakage Per Device Pin
Capacitance for SDA and SCL
External Termination Resistance
pull to V_DD = 2.5V ± 5% OR 3.3V ±
10%
(1)
(1) (2)
Pullup V_DD = 3.3V,
(1) (2) (3)
Pullup V_DD = 2.5V,
(1) (2) (3)
2.375
-200
SERIAL BUS INTERFACE TIMING SPECIFICATIONS. See Figure 8
FSMB
Bus Operating Frequency
(4)
10
TBUF
Bus Free Time Between Stop and
Start Condition
4.7
THD:STA
Hold time after (Repeated) Start
At I_PULLUP, Max
Condition. After this period, the first
4.0
clock is generated.
TSU:STA
Repeated Start Condition Setup
Time
4.7
TSU:STO
Stop Condition Setup Time
4.0
THD:DAT
Data Hold Time
300
TSU:DAT
Data Setup Time
250
T_TIMEOUT
Detect Clock Low Timeout
(4)
25
T_LOW
Clock Low Period
4.7
T_HIGH
Clock High Period
(4)
4.0
T_LOW:SEXT
Cumulative Clock Low Extend Time ⁽⁴⁾
(Slave Device)
t_F
Clock/Data Fall Time
(4)
t_R
Clock/Data Rise Time
(4)
t_POR
Time in which a device must be
(4)
operational after power-on reset
Typ
-15
2000
1000
www.ti.com
Max
0.8
3.6
3.6
+200
10
Units
V
V
mA
V
µA
µA
pF
Ω
Ω
100
kHz
µs
µs
µs
µs
ns
ns
35
ms
µs
50
µs
2
ms
300
ns
1000
ns
500
ms
(1) Recommended value. Parameter not tested in production.
(2) Recommended maximum capacitance load per bus segment is 400pF.
(3) Maximum termination voltage should be identical to the device supply voltage.
(4) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
Timing Diagrams
Figure 4. CML Output Transition Times
14
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