DS50EV401_15 Datasheet, PDF (9/19 Pages) Texas Instruments – DS50EV401 2.5 Gbps / 5.0 Gbps or 8.0 Gbps Quad Cable and Backplane Equalizer

DS50EV401
www.ti.com
SNLS288E – JANUARY 2008 – REVISED MARCH 2013
APPLICATION INFORMATION
GENERAL RECOMMENDATIONS
The DS50EV401 is a high performance device capable of delivering excellent performance. As with most CML
devices, it is recommended that AC coupling capacitors be used to ensure I/O compatibility with other devices. In
order to extract full performance from the device in a particular application, good high-speed design practices
must be followed. TI’s LVDS Owner's Manual (literature number SNLA187), provides detailed information about
managing signal integrity and power delivery to get the most from your design.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS
The CML inputs and outputs must have a controlled differential impedance of 100Ω. It is preferable to route CML
lines exclusively on one layer of the board, particularly for the input traces. The use of vias should be avoided if
possible. If vias must be used, they should be used sparingly and must be placed symmetrically for each side of
a given differential pair. Route the CML signals away from other signals and noise sources on the printed circuit
board. See AN-1187 (SNOA401) for additional information on WQFN packages.
PACKAGE FOOTPRINT / SOLDERING
See Application Note number 1187, “Leadless Leadframe Package” for information on PCB footprint and
soldering recommendations.
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the DS50EV401 is provided with an adequate power supply.
First, the supply (V_DD) and ground (GND) pins should be connected to power planes routed on adjacent layers of
the printed circuit board. The layer thickness of the dielectric should be minimized so that the V_DD and GND
planes create a low inductance supply with distributed capacitance. Second, careful attention to supply
bypassing through the proper use of bypass capacitors is required. A 0.1μF bypass capacitor should be
connected to each V_DD pin such that the capacitor is placed as close as possible to the DS50EV401. Smaller
body size capacitors can help facilitate proper component placement. Additionally, three capacitors with
capacitance in the range of 2.2 μF to 10 μF should be incorporated in the power supply bypassing design as
well. These capacitors can be either tantalum or an ultra-low ESR ceramic and should be placed as close as
possible to the DS50EV401.
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